From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-mm@kvack.org, Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers
Date: Mon, 24 Jun 2019 07:42:58 +0200 [thread overview]
Message-ID: <20190624054311.30256-5-hch@lst.de> (raw)
In-Reply-To: <20190624054311.30256-1-hch@lst.de>
When running in M-mode we still the S-mode plic handlers in the DT.
Ignore them by setting the maximum threshold.
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
drivers/irqchip/irq-sifive-plic.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index cf755964f2f8..c72c036aea76 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -244,6 +244,7 @@ static int __init plic_init(struct device_node *node,
struct plic_handler *handler;
irq_hw_number_t hwirq;
int cpu, hartid;
+ u32 threshold = 0;
if (of_irq_parse_one(node, i, &parent)) {
pr_err("failed to parse parent for context %d.\n", i);
@@ -266,10 +267,16 @@ static int __init plic_init(struct device_node *node,
continue;
}
+ /*
+ * When running in M-mode we need to ignore the S-mode handler.
+ * Here we assume it always comes later, but that might be a
+ * little fragile.
+ */
handler = per_cpu_ptr(&plic_handlers, cpu);
if (handler->present) {
pr_warn("handler already present for context %d.\n", i);
- continue;
+ threshold = 0xffffffff;
+ goto done;
}
handler->present = true;
@@ -279,8 +286,9 @@ static int __init plic_init(struct device_node *node,
handler->enable_base =
plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
+done:
/* priority must be > threshold to trigger an interrupt */
- writel(0, handler->hart_base + CONTEXT_THRESHOLD);
+ writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
plic_toggle(handler, hwirq, 0);
nr_handlers++;
--
2.20.1
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next prev parent reply other threads:[~2019-06-24 5:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-24 5:42 RISC-V nommu support v2 Christoph Hellwig
2019-06-24 5:42 ` [PATCH 01/17] mm: provide a print_vma_addr stub for !CONFIG_MMU Christoph Hellwig
2019-06-24 5:42 ` [PATCH 02/17] mm: stub out all of swapops.h " Christoph Hellwig
2019-06-24 5:42 ` [PATCH 03/17] mm/nommu: fix the MAP_UNINITIALIZED flag Christoph Hellwig
2019-06-24 5:42 ` Christoph Hellwig [this message]
2019-06-24 5:42 ` [PATCH 05/17] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-07-01 18:53 ` Atish Patra
2019-06-24 5:43 ` [PATCH 06/17] riscv: refactor the IPI code Christoph Hellwig
2019-06-24 5:43 ` [PATCH 07/17] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-07-01 18:37 ` Atish Patra
2019-06-24 5:43 ` [PATCH 08/17] riscv: improve the default power off implementation Christoph Hellwig
2019-07-01 21:07 ` Atish Patra
2019-06-24 5:43 ` [PATCH 09/17] riscv: provide a flat entry loader Christoph Hellwig
2019-06-24 5:43 ` [PATCH 10/17] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-07-01 21:15 ` Atish Patra
2019-06-24 5:43 ` [PATCH 11/17] riscv: provide native clint access for M-mode Christoph Hellwig
2019-06-24 5:43 ` [PATCH 12/17] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 13/17] riscv: poison SBI calls " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 14/17] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 15/17] riscv: use the correct interrupt levels " Christoph Hellwig
2019-06-24 5:43 ` [PATCH 16/17] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-07-01 21:26 ` Atish Patra
2019-07-08 8:26 ` Palmer Dabbelt
2019-08-13 15:40 ` Christoph Hellwig
2019-08-13 15:37 ` hch
2019-06-24 5:43 ` [PATCH 17/17] riscv: add nommu support Christoph Hellwig
2019-07-12 14:52 ` Vladimir Murzin
2019-06-24 11:47 ` RISC-V nommu support v2 Vladimir Murzin
2019-06-24 11:54 ` Christoph Hellwig
2019-06-24 13:08 ` Vladimir Murzin
2019-06-24 13:16 ` Christoph Hellwig
2019-06-25 7:31 ` Palmer Dabbelt
2019-06-25 12:37 ` Vladimir Murzin
2019-07-01 6:56 ` Christoph Hellwig
2019-07-01 16:06 ` Paul Walmsley
-- strict thread matches above, loose matches on Subject: below --
2019-06-10 22:16 RISC-V nommu support Christoph Hellwig
2019-06-10 22:16 ` [PATCH 04/17] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
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