From: Zong Li <zong.li@sifive.com>
To: corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH] riscv: gcov: enable gcov for RISC-V
Date: Thu, 2 Jan 2020 11:09:54 +0800 [thread overview]
Message-ID: <20200102030954.41225-1-zong.li@sifive.com> (raw)
This patch enables GCOV code coverage measurement on RISC-V.
Lightly tested on QEMU and Hifive Unleashed board, seems to work as
expected.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +-
arch/riscv/Kconfig | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 059d58a549c7..6fb2b0671994 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -23,7 +23,7 @@
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
- | riscv: | TODO |
+ | riscv: | ok |
| s390: | ok |
| sh: | ok |
| sparc: | TODO |
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d8efbaa78d67..a31169b02ec0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,7 @@ config RISCV
select SPARSEMEM_STATIC if 32BIT
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select HAVE_ARCH_MMAP_RND_BITS if MMU
+ select ARCH_HAS_GCOV_PROFILE_ALL
config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT
--
2.24.1
next reply other threads:[~2020-01-02 3:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 3:09 Zong Li [this message]
2020-01-02 3:37 ` [PATCH] riscv: gcov: enable gcov for RISC-V Anup Patel
2020-01-02 3:47 ` Zong Li
2020-01-02 14:59 ` Jonathan Corbet
2020-01-04 0:11 ` Paul Walmsley
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