From: Xianting Tian <xianting.tian@linux.alibaba.com>
To: crash-utility@redhat.com, mick@ics.forth.gr,
heinrich.schuchardt@canonical.com, guoren@kernel.org,
k-hagio-ab@nec.com, yixun.lan@gmail.com
Cc: linux-riscv@lists.infradead.org, kexec@lists.infradead.org,
hschauhan@nulltrace.org, huanyi.xj@alibaba-inc.com,
Xianting Tian <xianting.tian@linux.alibaba.com>
Subject: [Crash-utility][PATCH V2 8/9] RISCV64: Add 'mach' command support
Date: Mon, 1 Aug 2022 12:30:39 +0800 [thread overview]
Message-ID: <20220801043040.2003264-9-xianting.tian@linux.alibaba.com> (raw)
In-Reply-To: <20220801043040.2003264-1-xianting.tian@linux.alibaba.com>
With the patch we can get some basic machine state information,
crash> mach
MACHINE TYPE: riscv64
MEMORY SIZE: 1 GB
CPUS: 1
PROCESSOR SPEED: (unknown)
HZ: 250
PAGE SIZE: 4096
KERNEL STACK SIZE: 16384
Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
---
riscv64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/riscv64.c b/riscv64.c
index 1506e05..dfb3950 100644
--- a/riscv64.c
+++ b/riscv64.c
@@ -115,10 +115,53 @@ static void riscv64_get_struct_page_size(struct machine_specific *ms)
free(string);
}
+/*
+ * "mach" command output.
+ */
+static void
+riscv64_display_machine_stats(void)
+{
+ struct new_utsname *uts;
+ char buf[BUFSIZE];
+ ulong mhz;
+
+ uts = &kt->utsname;
+
+ fprintf(fp, " MACHINE TYPE: %s\n", uts->machine);
+ fprintf(fp, " MEMORY SIZE: %s\n", get_memory_size(buf));
+ fprintf(fp, " CPUS: %d\n", get_cpus_to_display());
+ fprintf(fp, " PROCESSOR SPEED: ");
+ if ((mhz = machdep->processor_speed()))
+ fprintf(fp, "%ld Mhz\n", mhz);
+ else
+ fprintf(fp, "(unknown)\n");
+ fprintf(fp, " HZ: %d\n", machdep->hz);
+ fprintf(fp, " PAGE SIZE: %d\n", PAGESIZE());
+ fprintf(fp, " KERNEL STACK SIZE: %ld\n", STACKSIZE());
+}
+
static void
riscv64_cmd_mach(void)
{
- /* TODO: */
+ int c;
+
+ while ((c = getopt(argcnt, args, "cmo")) != EOF) {
+ switch (c) {
+ case 'c':
+ case 'm':
+ case 'o':
+ option_not_supported(c);
+ break;
+ default:
+ argerrs++;
+ break;
+ }
+ }
+
+ if (argerrs)
+ cmd_usage(pc->curcmd, SYNOPSIS);
+
+ riscv64_display_machine_stats();
}
static int
--
2.17.1
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next prev parent reply other threads:[~2022-08-01 4:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-01 4:30 [Crash-utility][PATCH V2 0/9] Support RISCV64 arch and common commands Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 1/9] Add RISCV64 framework code support Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 2/9] RISCV64: Make crash tool enter command line and support some commands Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 3/9] RISCV64: Add 'dis' command support Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 4/9] RISCV64: Add 'irq' " Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 5/9] RISCV64: Add 'bt' " Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 6/9] RISCV64: Add 'help -r' " Xianting Tian
2022-08-01 4:30 ` [Crash-utility][PATCH V2 7/9] RISCV64: Add 'help -m/M' " Xianting Tian
2022-08-01 4:30 ` Xianting Tian [this message]
2022-08-01 4:30 ` [Crash-utility][PATCH V2 9/9] RISCV64: Add the implementation of symbol verify Xianting Tian
2022-08-05 2:36 ` [Crash-utility][PATCH V2 0/9] Support RISCV64 arch and common commands HAGIO KAZUHITO(萩尾 一仁)
2022-08-05 6:19 ` Xianting Tian
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