From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v7 22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core
Date: Sat, 1 Apr 2023 19:19:34 +0800 [thread overview]
Message-ID: <20230401111934.130844-23-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20230401111934.130844-1-hal.feng@starfivetech.com>
The S7 core has no L1 data cache and MMU, so delete some
related properties.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..4c5fdb905da8 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -20,21 +20,12 @@ cpus {
S7_0: cpu@0 {
compatible = "sifive,s7", "riscv";
reg = <0>;
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <8192>;
- d-tlb-sets = <1>;
- d-tlb-size = <40>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
- i-tlb-sets = <1>;
- i-tlb-size = <40>;
- mmu-type = "riscv,sv39";
next-level-cache = <&ccache>;
riscv,isa = "rv64imac_zba_zbb";
- tlb-split;
status = "disabled";
cpu0_intc: interrupt-controller {
--
2.38.1
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next prev parent reply other threads:[~2023-04-01 11:20 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 11:19 [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-04-01 11:19 ` [PATCH v7 01/22] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-04-01 11:19 ` [PATCH v7 02/22] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-04-01 11:19 ` [PATCH v7 03/22] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-04-05 11:48 ` Heiko Stübner
2023-04-01 11:19 ` [PATCH v7 04/22] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-04-01 11:19 ` [PATCH v7 05/22] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-04-01 11:19 ` [PATCH v7 06/22] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-04-01 11:19 ` [PATCH v7 07/22] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-04-01 11:19 ` [PATCH v7 08/22] reset: Create subdirectory for StarFive drivers Hal Feng
2023-04-01 11:19 ` [PATCH v7 09/22] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-04-01 11:19 ` [PATCH v7 10/22] reset: starfive: Extract the " Hal Feng
2023-04-01 11:19 ` [PATCH v7 11/22] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-04-01 11:19 ` [PATCH v7 12/22] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-04-01 11:19 ` [PATCH v7 13/22] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-04-01 11:19 ` [PATCH v7 14/22] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-04-01 11:19 ` [PATCH v7 15/22] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-04-01 11:19 ` [PATCH v7 16/22] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-04-01 11:19 ` [PATCH v7 17/22] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-04-01 11:19 ` [PATCH v7 18/22] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-04-01 11:19 ` [PATCH v7 19/22] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-05-07 10:03 ` Shengyu Qu
2023-06-01 3:39 ` Hal Feng
2023-04-01 11:19 ` [PATCH v7 20/22] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-04-01 11:19 ` [PATCH v7 21/22] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-04-04 18:38 ` Shengyu Qu
2023-04-05 1:40 ` Hal Feng
2023-04-01 11:19 ` Hal Feng [this message]
2023-04-02 19:19 ` [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-04-03 7:30 ` Hal Feng
2023-04-03 7:47 ` Conor Dooley
2023-04-05 14:40 ` Emil Renner Berthing
2023-04-05 21:30 ` Conor Dooley
2023-04-06 7:03 ` Hal Feng
2023-04-11 21:35 ` Conor Dooley
2023-04-12 2:12 ` Hal Feng
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