From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org
Subject: [PATCH RESEND] dt-bindings: riscv: add sv57 mmu-type
Date: Mon, 24 Apr 2023 18:05:43 +0100 [thread overview]
Message-ID: <20230424-rival-habitual-478567c516f0@spud> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
Dumping the dtb from new versions of QEMU warns that sv57 is an
undocumented mmu-type. The kernel has supported sv57 for about a year,
so bring it into the fold.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Resending with the missing CCs.
Palmer, you can take this for 6.4 if you want, otherwise I'll grab it
after the merge window. I doubt there's a rush when it's been missing
for a year or so.
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 4c7ce4a37052..25d6e8dbffb8 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -66,6 +66,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
+ - riscv,sv57
- riscv,none
riscv,cbom-block-size:
--
2.39.2
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next reply other threads:[~2023-04-24 17:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-24 17:05 Conor Dooley [this message]
2023-04-25 18:56 ` [PATCH RESEND] dt-bindings: riscv: add sv57 mmu-type Rob Herring
2023-04-26 14:30 ` Palmer Dabbelt
2023-04-26 15:57 ` Palmer Dabbelt
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