From: Andrew Jones <ajones@ventanamicro.com>
To: Haibo Xu <xiaobo55x@gmail.com>
Cc: Haibo Xu <haibo1.xu@intel.com>,
maz@kernel.org, oliver.upton@linux.dev, seanjc@google.com,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Shuah Khan <shuah@kernel.org>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
David Matlack <dmatlack@google.com>,
Ben Gardon <bgardon@google.com>,
Vipin Sharma <vipinsh@google.com>,
Colton Lewis <coltonlewis@google.com>,
kvm@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v2 11/11] KVM: riscv: selftests: Add get-reg-list test
Date: Thu, 8 Jun 2023 11:58:47 +0200 [thread overview]
Message-ID: <20230608-344953a953eeb63ef6c26fb8@orel> (raw)
In-Reply-To: <CAJve8okR_iH4vF9DV9zTkDaeYe25kP7KUcKQphmjG5q-iVb-KA@mail.gmail.com>
On Thu, Jun 08, 2023 at 05:45:21PM +0800, Haibo Xu wrote:
> On Fri, May 26, 2023 at 1:18 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
>
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(sstatus),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(sie),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(stvec),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(sscratch),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(sepc),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(scause),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(stval),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(sip),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(satp),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_REG(scounteren),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_F,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I,
> > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M,
> >
> > I think all the above should have the size KVM_REG_SIZE_ULONG. Please also
> > test with a 32-bit host.
> >
>
> Hi Andrew,
>
> Just noticed the RISC-V 32-bit kvm selftests was not supported currently.
Oh, right.
> Even though I tried to remove the below check for 32-bit, there were
> still many warning and error messages during compiling.
> It seems 32-bit KVM selftests was not supported either for ARM/x86. Do
> we have a plan to support it on risc-v?
No plan and, if there was, it would be super low priority. So for stuff
like using KVM_REG_SIZE_ULONG, we'll just have to try and get it right
without testing. If somebody adds 32-bit support to these tests someday,
then, hopefully, it'll just work (I'm allowed one overly optimistic
comment per day).
Thanks,
drew
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next prev parent reply other threads:[~2023-06-08 9:58 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-25 7:38 [PATCH v2 00/11] RISCV: Add KVM_GET_REG_LIST API Haibo Xu
2023-05-25 7:38 ` [PATCH v2 01/11] KVM: arm64: selftests: Replace str_with_index with strdup_printf Haibo Xu
2023-05-25 7:38 ` [PATCH v2 02/11] KVM: arm64: selftests: Drop SVE cap check in print_reg Haibo Xu
2023-05-25 7:38 ` [PATCH v2 03/11] KVM: arm64: selftests: Remove print_reg's dependency on vcpu_config Haibo Xu
2023-05-25 7:38 ` [PATCH v2 04/11] KVM: arm64: selftests: Rename vcpu_config and add to kvm_util.h Haibo Xu
2023-05-25 7:38 ` [PATCH v2 05/11] KVM: arm64: selftests: Delete core_reg_fixup Haibo Xu
2023-05-25 7:38 ` [PATCH v2 06/11] KVM: arm64: selftests: Split get-reg-list test code Haibo Xu
2023-05-25 7:38 ` [PATCH v2 07/11] KVM: arm64: selftests: Finish generalizing get-reg-list Haibo Xu
2023-05-25 7:38 ` [PATCH v2 08/11] KVM: riscv: Add KVM_GET_REG_LIST API support Haibo Xu
2023-05-25 7:38 ` [PATCH v2 09/11] KVM: riscv: selftests: Make check_supported arch specific Haibo Xu
2023-05-25 16:40 ` Andrew Jones
2023-05-26 7:50 ` Haibo Xu
2023-05-26 8:44 ` Andrew Jones
2023-05-27 2:26 ` Haibo Xu
2023-05-25 7:38 ` [PATCH v2 10/11] KVM: riscv: selftests: Skip some registers set operation Haibo Xu
2023-05-25 16:41 ` Andrew Jones
2023-05-25 7:38 ` [PATCH v2 11/11] KVM: riscv: selftests: Add get-reg-list test Haibo Xu
2023-05-25 17:18 ` Andrew Jones
2023-05-27 4:39 ` Haibo Xu
2023-05-29 7:08 ` Andrew Jones
2023-05-29 12:20 ` Haibo Xu
2023-06-08 9:45 ` Haibo Xu
2023-06-08 9:58 ` Andrew Jones [this message]
2023-06-09 1:20 ` Haibo Xu
2023-05-25 17:20 ` [PATCH v2 00/11] RISCV: Add KVM_GET_REG_LIST API Andrew Jones
2023-05-26 6:22 ` Haibo Xu
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