From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
Date: Sun, 18 Jun 2023 00:15:27 +0800 [thread overview]
Message-ID: <20230617161529.2092-7-jszhang@kernel.org> (raw)
In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org>
Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.
Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/thead/Makefile | 2 +
.../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++
.../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++
4 files changed, 73 insertions(+)
create mode 100644 arch/riscv/boot/dts/thead/Makefile
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f0d9f89054f8..1e884868ccba 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -2,6 +2,7 @@
subdir-y += allwinner
subdir-y += sifive
subdir-y += starfive
+subdir-y += thead
subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
new file mode 100644
index 000000000000..e311fc9a5939
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
new file mode 100644
index 000000000000..4b0249ac710f
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+ model = "Sipeed Lichee Module 4A";
+ compatible = "sipeed,lichee-module-4a", "thead,th1520";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x2 0x00000000>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&osc_32k {
+ clock-frequency = <32768>;
+};
+
+&apb_clk {
+ clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+ clock-frequency = <100000000>;
+};
+
+&dmac0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
new file mode 100644
index 000000000000..a1248b2ee3a3
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include "th1520-lichee-module-4a.dtsi"
+
+/ {
+ model = "Sipeed Lichee Pi 4A";
+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.40.0
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next prev parent reply other threads:[~2023-06-17 16:27 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang [this message]
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-18 16:14 ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 21:01 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:52 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 14:32 ` Drew Fustini
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 14:58 ` Jisheng Zhang
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 15:00 ` Jisheng Zhang
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:29 ` Xi Ruoyao
2023-07-28 7:04 ` Drew Fustini
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 17:53 ` Drew Fustini
2023-07-29 7:11 ` Xi Ruoyao
2023-07-28 0:11 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:46 ` Conor Dooley
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