[PATCH v3] RISC-V: Document that V registers are clobbered on syscalls

[Palmer Dabbelt <palmer@rivosinc.com>]

This is included in the ISA manual, but it's pretty common for bits of
the ISA manual that are actually ABI to change.  So let's document it
explicitly.

Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 Documentation/riscv/vector.rst | 8 ++++++++
 1 file changed, 8 insertions(+)
---
Changes since v2 <20230619180411.12946-1-palmer@rivosinc.com>:
* Add a link to the V spec's calling convention doc.

Changes since v1 <20230614163534.18668-1-palmer@rivosinc.com>:
* Remove the code change, just update the documentation.  We might still
  want to do something in the code, but that's still under discussion
  so let's get the docs sorted out for now.

diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
index 48f189d79e41..165b7ed0ac4f 100644
--- a/Documentation/riscv/vector.rst
+++ b/Documentation/riscv/vector.rst
@@ -130,3 +130,11 @@ processes in form of sysctl knob:
 
     Modifying the system default enablement status does not affect the enablement
     status of any existing process of thread that do not make an execve() call.
+
+3.  Vector Register State Across System Calls
+---------------------------------------------
+
+As indicated by version 1.0 of the V extension [1], vector registers are
+clobbered by system calls.
+
+1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc
-- 
2.40.1


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