From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: linux-riscv@lists.infradead.org, samuel@sholland.org,
guoren@kernel.org, christoph.muellner@vrull.eu, heiko@sntech.de,
conor.dooley@microchip.com, linux-kernel@vger.kernel.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: [PATCH v2 0/2] RISC-V: T-Head vector handling
Date: Fri, 23 Jun 2023 01:13:02 +0200 [thread overview]
Message-ID: <20230622231305.631331-1-heiko@sntech.de> (raw)
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
As is widely known the T-Head C9xx cores used for example in the
Allwinner D1 implement an older non-ratified variant of the vector spec.
While userspace will probably have a lot more problems implementing
support for both, on the kernel side the needed changes are actually
somewhat small'ish and can be handled via alternatives somewhat nicely.
With this patchset I could run the same userspace program (picked from
some riscv-vector-test repository) that does some vector additions on
both qemu and a d1-nezha board. On both platforms it ran sucessfully and
even produced the same results.
As can be seen in the todo list, there are 2 places where the changed
SR_VS location still needs to be handled in the next revision
(assembly + ALTERNATIVES + constants + probably stringify resulted in
some grey hair so far already)
ToDo:
- follow along with the base vector patchset
- handle SR_VS access in _save_context and _secondary_start_sbi
changes since v1:
- rebase on top of the merged vector patchset
- add separate patch for "has_vector()" variable
- a number of cleanups
- a comment that T-Head cores do not seem to implement the
vxsat and vxrm fields in the fcsr register
Heiko Stuebner (3):
RISC-V: define the elements of the VCSR vector CSR
RISC-V: move vector-available status into a dedicated variable
RISC-V: add T-Head vector errata handling
arch/riscv/Kconfig.errata | 13 +++
arch/riscv/errata/thead/errata.c | 32 ++++++
arch/riscv/include/asm/csr.h | 29 +++++-
arch/riscv/include/asm/errata_list.h | 45 ++++++++-
arch/riscv/include/asm/vector.h | 144 +++++++++++++++++++++++++--
arch/riscv/kernel/setup.c | 6 ++
arch/riscv/kernel/vector.c | 10 +-
7 files changed, 261 insertions(+), 18 deletions(-)
--
2.39.2
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next reply other threads:[~2023-06-22 23:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 23:13 Heiko Stuebner [this message]
2023-06-22 23:13 ` [PATCH v2 1/3] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Heiko Stuebner
2023-06-23 9:19 ` Conor Dooley
2023-06-23 13:47 ` kernel test robot
2023-06-22 23:13 ` [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-06-23 3:11 ` kernel test robot
2023-06-23 9:49 ` Conor Dooley
2023-06-23 10:40 ` Heiko Stübner
2023-06-23 11:44 ` Conor Dooley
2023-06-24 5:18 ` Stefan O'Rear
2023-06-24 10:59 ` Andrew Jones
2023-06-28 16:07 ` Andy Chiu
2023-06-23 13:47 ` kernel test robot
2023-06-27 15:21 ` Rémi Denis-Courmont
2023-06-27 16:12 ` Conor Dooley
2023-06-28 14:23 ` Palmer Dabbelt
2023-06-29 16:06 ` Rémi Denis-Courmont
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