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From: Conor Dooley <conor@kernel.org>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Inochi Amaoto <inochiama@outlook.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Nikita Shubin <n.shubin@yadro.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH V3] perf vendor events riscv: add T-HEAD C9xx JSON file
Date: Sat, 24 Jun 2023 09:54:50 +0100	[thread overview]
Message-ID: <20230624-supermom-disparity-37546ffed0a4@spud> (raw)
In-Reply-To: <CAM9d7cis-rb0fozK+T6R8MCEcT0ZF=RRNpv1qAWsLkMfsG6KxA@mail.gmail.com>


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On Fri, Jun 23, 2023 at 09:35:01PM -0700, Namhyung Kim wrote:
> On Fri, Jun 23, 2023 at 6:33 PM Inochi Amaoto <inochiama@outlook.com> wrote:

> >
> > As for c9xx wildcard, the T-HEAD provides a `MCPUID` vendor CSR to allow
> > its CKLINK to get the detail CPU info. The format of this CSR are:
> >
> > ------------------------------------------------
> > |31   28|27  26|25    22|21   18|17    8|7    0|
> > | index | WLRL | family | class | model | WLRL |
> > ------------------------------------------------
> >
> > And for C9xx series (only index 0000 is vaild for us, as `MCPUID` also
> > provides other index).
> >
> > | 0000 | xx | 0100 | class | xxxxxxxxxx | xxxxxxxx |
> >
> > The class codes are:
> >
> > C910: 0011
> > c906: 0100
> >
> > The CSR is a M-mode only CSR, so now I'm exploring a clean way to
> > integrate this CSR into the kernel. Any advice?

See for example how riscv_cpuinfo_starting() reads mvendorid & Co.

> I don't know about the details.  Is this CSR available from user space?
> If not, you could add it somewhere in the sysfs.

Machine mode is the highest privilege level, Supervisor mode is next &
User mode is the lowest. Typically the kernel runs in Supervisor mode.

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  parent reply	other threads:[~2023-06-24  8:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-17  7:12 [PATCH V3] perf vendor events riscv: add T-HEAD C9xx JSON file Inochi Amaoto
2023-05-18 12:09 ` Nikita Shubin
2023-05-18  9:48   ` Inochi Amaoto
2023-06-24  0:17     ` Namhyung Kim
2023-06-24  1:32       ` Inochi Amaoto
2023-06-24  4:35         ` Namhyung Kim
2023-06-24  6:42           ` Inochi Amaoto
2023-06-24  8:54           ` Conor Dooley [this message]
2023-06-26 23:14             ` Namhyung Kim
2023-06-27  8:40   ` Atish Patra
2023-06-27 11:51     ` Nikita Shubin
2023-06-22  0:11 ` Palmer Dabbelt

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