Re: [PATCH v2 2/6] RISC-V: Enable cbo.zero in usermode

[Andrew Jones <ajones@ventanamicro.com>]

On Thu, Aug 31, 2023 at 05:24:41PM +0100, Conor Dooley wrote:
> On Wed, Aug 30, 2023 at 06:49:57PM +0200, Andrew Jones wrote:
> > When Zicboz is present, enable its instruction (cbo.zero) in
> > usermode by setting its respective senvcfg bit. We don't bother
> > trying to set this bit per-task, which would also require an
> > interface for tasks to request enabling and/or disabling. Instead,
> > permanently set the bit for each hart which has the extension when
> > bringing it online.
> > 
> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> > ---
> >  arch/riscv/include/asm/cpufeature.h |  2 ++
> >  arch/riscv/include/asm/csr.h        |  1 +
> >  arch/riscv/include/asm/hwcap.h      | 16 ++++++++++++++++
> >  arch/riscv/kernel/cpufeature.c      |  6 ++++++
> >  arch/riscv/kernel/setup.c           |  4 ++++
> >  arch/riscv/kernel/smpboot.c         |  4 ++++
> >  6 files changed, 33 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 23fed53b8815..788fd575c21a 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -30,4 +30,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
> >  /* Per-cpu ISA extensions. */
> >  extern struct riscv_isainfo hart_isa[NR_CPUS];
> >  
> > +void riscv_user_isa_enable(void);
> > +
> >  #endif
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index 7bac43a3176e..e187e76e3df4 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -273,6 +273,7 @@
> >  #define CSR_SIE			0x104
> >  #define CSR_STVEC		0x105
> >  #define CSR_SCOUNTEREN		0x106
> > +#define CSR_SENVCFG		0x10a
> >  #define CSR_SSCRATCH		0x140
> >  #define CSR_SEPC		0x141
> >  #define CSR_SCAUSE		0x142
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index f041bfa7f6a0..66178dbd0045 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -66,6 +66,7 @@
> >  #ifndef __ASSEMBLY__
> >  
> >  #include <linux/jump_label.h>
> > +#include <asm/cpufeature.h>
> >  
> >  unsigned long riscv_get_elf_hwcap(void);
> >  
> > @@ -130,6 +131,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
> >  	return true;
> >  }
> >  
> > +static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
> > +{
> > +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
> > +		return true;
> 
> It'd have been nice to put the explanation for this into the commit
> message I think, but w/e. Do it if there's a v3 I guess.

Do you mean the "why gate on the alternative config" explanation? If so, I
can certainly do that for v3.

> 
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
drew

> 
> Thanks,
> Conor.
> 
> > +
> > +	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> > +}
> > +
> > +static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
> > +{
> > +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
> > +		return true;
> > +
> > +	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
> > +}
> >  #endif
> >  
> >  #endif /* _ASM_RISCV_HWCAP_H */
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 31843e9cc80c..a33cf7c89d9e 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -391,6 +391,12 @@ unsigned long riscv_get_elf_hwcap(void)
> >  	return hwcap;
> >  }
> >  
> > +void riscv_user_isa_enable(void)
> > +{
> > +	if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
> > +		csr_set(CSR_SENVCFG, ENVCFG_CBZE);
> > +}
> > +
> >  #ifdef CONFIG_RISCV_ALTERNATIVE
> >  /*
> >   * Alternative patch sites consider 48 bits when determining when to patch
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 971fe776e2f8..2f053f0763a1 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -25,6 +25,7 @@
> >  #include <asm/acpi.h>
> >  #include <asm/alternative.h>
> >  #include <asm/cacheflush.h>
> > +#include <asm/cpufeature.h>
> >  #include <asm/cpu_ops.h>
> >  #include <asm/early_ioremap.h>
> >  #include <asm/pgtable.h>
> > @@ -308,9 +309,12 @@ void __init setup_arch(char **cmdline_p)
> >  	riscv_fill_hwcap();
> >  	init_rt_signal_env();
> >  	apply_boot_alternatives();
> > +
> >  	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> >  	    riscv_isa_extension_available(NULL, ZICBOM))
> >  		riscv_noncoherent_supported();
> > +
> > +	riscv_user_isa_enable();
> >  }
> >  
> >  static int __init topology_init(void)
> > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > index f4d6acb38dd0..502b04abda0b 100644
> > --- a/arch/riscv/kernel/smpboot.c
> > +++ b/arch/riscv/kernel/smpboot.c
> > @@ -25,6 +25,8 @@
> >  #include <linux/of.h>
> >  #include <linux/sched/task_stack.h>
> >  #include <linux/sched/mm.h>
> > +
> > +#include <asm/cpufeature.h>
> >  #include <asm/cpu_ops.h>
> >  #include <asm/irq.h>
> >  #include <asm/mmu_context.h>
> > @@ -252,6 +254,8 @@ asmlinkage __visible void smp_callin(void)
> >  			elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
> >  	}
> >  
> > +	riscv_user_isa_enable();
> > +
> >  	/*
> >  	 * Remote TLB flushes are ignored while the CPU is offline, so emit
> >  	 * a local TLB flush right now just in case.
> > -- 
> > 2.41.0
> > 
> > 
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv



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