From: Conor Dooley <conor@kernel.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, suagrfillet@gmail.com
Subject: Re: [PATCH v2 1/2] RISC-V: Provide pgtable_l5_enabled on rv32
Date: Thu, 31 Aug 2023 17:27:37 +0100 [thread overview]
Message-ID: <20230831-mating-marital-9963d47f361b@spud> (raw)
In-Reply-To: <20230830044129.11481-2-palmer@rivosinc.com>
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On Tue, Aug 29, 2023 at 09:39:19PM -0700, Palmer Dabbelt wrote:
> A few of the other page table level helpers are defined on rv32, but not
> pgtable_l5_enabled. This adds the definition as a constant and converts
> pgtable_l4_enabled to a constant as well.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> arch/riscv/include/asm/pgtable-32.h | 3 +++
> arch/riscv/include/asm/pgtable.h | 1 -
> arch/riscv/mm/init.c | 2 ++
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 59ba1fbaf784..49c42016f0ed 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -33,4 +33,7 @@
> _PAGE_WRITE | _PAGE_EXEC | \
> _PAGE_USER | _PAGE_GLOBAL))
>
> +static const __maybe_unused int pgtable_l4_enabled = 0;
> +static const __maybe_unused int pgtable_l5_enabled = 0;
FYI the automation complains:
ERROR: do not initialise statics to 0
> +
> #endif /* _ASM_RISCV_PGTABLE_32_H */
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 75970ee2bda2..dae884f52cc1 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -878,7 +878,6 @@ extern uintptr_t _dtb_early_pa;
> #define dtb_early_pa _dtb_early_pa
> #endif /* CONFIG_XIP_KERNEL */
> extern u64 satp_mode;
> -extern bool pgtable_l4_enabled;
>
> void paging_init(void);
> void misc_mem_init(void);
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 70fb31960b63..25ff8864e9bf 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -48,10 +48,12 @@ u64 satp_mode __ro_after_init = SATP_MODE_32;
> #endif
> EXPORT_SYMBOL(satp_mode);
>
> +#ifdef CONFIG_64BIT
> bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
> bool pgtable_l5_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
> EXPORT_SYMBOL(pgtable_l4_enabled);
> EXPORT_SYMBOL(pgtable_l5_enabled);
> +#endif
>
> phys_addr_t phys_ram_base __ro_after_init;
> EXPORT_SYMBOL(phys_ram_base);
> --
> 2.41.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-08-31 16:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-30 4:39 [PATCH v2 0/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
2023-08-30 4:39 ` [PATCH v2 1/2] RISC-V: Provide pgtable_l5_enabled on rv32 Palmer Dabbelt
2023-08-31 16:27 ` Conor Dooley [this message]
2023-08-30 4:39 ` [PATCH v2 2/2] riscv: correct pt_level name via pgtable_l5/4_enabled Palmer Dabbelt
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