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From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
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Subject: [PATCH v6 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520
Date: Mon, 25 Dec 2023 18:33:06 +0800	[thread overview]
Message-ID: <20231225103308.1557548-15-peterlin@andestech.com> (raw)
In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com>

xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes v4 -> v5:
  - New patch
Changes v5 -> v6:
  - Include Conor's Acked-by
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ba4d2c673ac8..2dad2b22824a 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -22,7 +22,7 @@ c910_0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -46,7 +46,7 @@ c910_1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -70,7 +70,7 @@ c910_2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -94,7 +94,7 @@ c910_3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadpmu";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
-- 
2.34.1


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  parent reply	other threads:[~2023-12-25 10:35 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-25 10:32 [PATCH v6 00/16] Support Andes PMU extension Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2023-12-25 10:32 ` [PATCH v6 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2023-12-25 10:33 ` Yu Chien Peter Lin [this message]
2023-12-25 10:33 ` [PATCH v6 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2023-12-25 10:33 ` [PATCH v6 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2023-12-25 21:06 ` [PATCH v6 00/16] Support Andes PMU extension Lad, Prabhakar
2023-12-26  2:59   ` Yu-Chien Peter Lin

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