From: Andrew Jones <ajones@ventanamicro.com>
To: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Cc: aou@eecs.berkeley.edu, rafael.j.wysocki@intel.com,
linux-kernel@vger.kernel.org, conor.dooley@microchip.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org
Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V
Date: Tue, 2 Jan 2024 16:39:06 +0100 [thread overview]
Message-ID: <20240102-1ddc9ec273fded1548ee586d@orel> (raw)
In-Reply-To: <20231229065405.235625-2-jeeheng.sia@starfivetech.com>
On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote:
> The ACPI SPCR code has been used to enable console output for ARM64 and
> X86. The same code can be reused for RISC-V.
>
> Vendor will enable/disable the SPCR table in the firmware based on the
> platform design. However, in cases where the SPCR table is not usable,
> a kernel parameter could be used to specify the preferred console.
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> ---
> arch/riscv/kernel/acpi.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> index e619edc8b0cc..5ec2fdf9e09f 100644
> --- a/arch/riscv/kernel/acpi.c
> +++ b/arch/riscv/kernel/acpi.c
> @@ -18,6 +18,7 @@
> #include <linux/io.h>
> #include <linux/memblock.h>
> #include <linux/pci.h>
> +#include <linux/serial_core.h>
>
> int acpi_noirq = 1; /* skip ACPI IRQ initialization */
> int acpi_disabled = 1;
> @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void)
> if (!param_acpi_force)
> disable_acpi();
> }
> +
> + if (!acpi_disabled)
> + acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when
acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that
not necessary for RISC-V?
Thanks,
drew
> }
>
> static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> --
> 2.34.1
>
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next prev parent reply other threads:[~2024-01-02 15:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-29 6:54 [RFC v1 0/1] Enable SPCR table for console output on RISC-V Sia Jee Heng
2023-12-29 6:54 ` [RFC v1 1/1] RISC-V: ACPI: " Sia Jee Heng
2024-01-02 15:39 ` Andrew Jones [this message]
2024-01-05 12:12 ` JeeHeng Sia
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