From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org
Cc: conor@kernel.org, "Conor Dooley" <conor.dooley@microchip.com>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Wedson Almeida Filho" <wedsonaf@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Nathan Chancellor" <nathan@kernel.org>,
"Nick Desaulniers" <ndesaulniers@google.com>,
rust-for-linux@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, llvm@lists.linux.dev
Subject: [PATCH v3 0/1] RISC-V: enable rust
Date: Tue, 9 Apr 2024 18:25:15 +0100 [thread overview]
Message-ID: <20240409-unsaddle-skittle-c93eb77732bb@spud> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
I've intentionally not turned on the gcc support, as discussed on
v1. I've also switched over to using the target, but it is a bit heavier
than the one arm64 seems to be using. RISC-V has fewer targets available
and this was the closest. I preserved the redzone disabling, just moved
into the Makefile. Any comment from Gary or the LLVM lads on the target
would be great I think:
https://github.com/rust-lang/rust/blob/master/compiler/rustc_target/src/spec/targets/riscv64imac_unknown_none_elf.rs
arm64 is using:
https://github.com/rust-lang/rust/blob/master/compiler/rustc_target/src/spec/targets/aarch64_unknown_none.rs
I was gonna send this yesterday, but found out last minute I had invalid
code in the target generation script. The kernel test robot had given my
branch the global all-clear - the rust coverage with all the
"depends on !FOO" must really limit the build coverage. I built for x86
with rust enabled locally this time to make sure..
As this as lifted from the state of the Rust-for-Linux tree, the commit
messages from there cannot be preserved, so these patches have commit
messages that I wrote.
I've tested this on Icicle, and the modules seem to work as expected.
Unfortunately there appear to be implicit 32-bit divisions (or similar)
in core Rust code, so, as in the downstream Rust-for-Linux tree, Rust is
only enabled for 64-bit.
Thanks,
Conor.
Changes in v3:
- Use a builtin target and modify it in kbuild
- Drop the kCFI patch, that's been merged independently
Changes in v2:
- Rebase, since a good bit of time has passed!
- Add the extra patch, disabling when CFI_CLANG is enabled.
Changes in v1:
- rebase on v6.3-rc1
- resort the `um` entry in the arch-support table while adding RISC-V
to it
- drop 32-bit bits
- have another crack at assigning authorship
Changes in RFC-RESEND:
- fix the asymmetrical additions in the Makefile bits
- add cc-cover to my git send-email command...
CC: Miguel Ojeda <ojeda@kernel.org>
CC: Alex Gaynor <alex.gaynor@gmail.com>
CC: Wedson Almeida Filho <wedsonaf@gmail.com>
CC: Boqun Feng <boqun.feng@gmail.com>
CC: Gary Guo <gary@garyguo.net>
CC: Björn Roy Baron <bjorn3_gh@protonmail.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: Nathan Chancellor <nathan@kernel.org>
CC: Nick Desaulniers <ndesaulniers@google.com>
CC: rust-for-linux@vger.kernel.org
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-riscv@lists.infradead.org
CC: llvm@lists.linux.dev
Miguel Ojeda (1):
RISC-V: enable building 64-bit kernels with rust support
Documentation/rust/arch-support.rst | 1 +
arch/riscv/Kconfig | 1 +
arch/riscv/Makefile | 7 +++++++
scripts/generate_rust_target.rs | 6 ++++++
4 files changed, 15 insertions(+)
--
2.43.0
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next reply other threads:[~2024-04-09 17:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-09 17:25 Conor Dooley [this message]
2024-04-09 17:25 ` [PATCH v3 1/1] RISC-V: enable building 64-bit kernels with rust support Conor Dooley
2024-04-17 14:00 ` Gary Guo
2024-04-10 13:22 ` [PATCH v3 0/1] RISC-V: enable rust Björn Töpel
2024-04-10 14:20 ` patchwork-bot+linux-riscv
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