From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH 2/3] riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
Date: Fri, 3 Jul 2020 16:57:54 +0800 [thread overview]
Message-ID: <25223adbad5badb3cd0000df078b407bafc129fd.1593766028.git.zong.li@sifive.com> (raw)
In-Reply-To: <cover.1593766028.git.zong.li@sifive.com>
AT_VECTOR_SIZE_ARCH should be defined with the maximum number of
NEW_AUX_ENT entries that ARCH_DLINFO can contain, but it wasn't defined
for RISC-V at all even though ARCH_DLINFO will contain one NEW_AUX_ENT
for the VDSO address.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
arch/riscv/include/uapi/asm/auxvec.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h
index d86cb17bbabe..22e0ae888406 100644
--- a/arch/riscv/include/uapi/asm/auxvec.h
+++ b/arch/riscv/include/uapi/asm/auxvec.h
@@ -10,4 +10,7 @@
/* vDSO location */
#define AT_SYSINFO_EHDR 33
+/* entries in ARCH_DLINFO */
+#define AT_VECTOR_SIZE_ARCH 1
+
#endif /* _UAPI_ASM_RISCV_AUXVEC_H */
--
2.27.0
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next prev parent reply other threads:[~2020-07-03 8:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 8:57 [PATCH 0/3] Get cache information from userland Zong Li
2020-07-03 8:57 ` [PATCH 1/3] riscv: Set more data to cacheinfo Zong Li
2020-08-20 20:44 ` Palmer Dabbelt
2020-07-03 8:57 ` Zong Li [this message]
2020-08-20 20:44 ` [PATCH 2/3] riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO Palmer Dabbelt
2020-07-03 8:57 ` [PATCH 3/3] riscv: Add cache information in AUX vector Zong Li
2020-08-20 20:44 ` Palmer Dabbelt
2020-07-27 3:03 ` [PATCH 0/3] Get cache information from userland Zong Li
2020-08-20 20:45 ` Palmer Dabbelt
2020-08-27 8:22 ` Zong Li
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