From: Mason Huo <mason.huo@starfivetech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Emil Renner Berthing <kernel@esmil.dk>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Shengyu Qu <wiagn233@outlook.com>, <linux-pm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
Date: Wed, 12 Apr 2023 10:35:52 +0800 [thread overview]
Message-ID: <2f5b4e94-0476-83df-0b18-a6b2ba1ea896@starfivetech.com> (raw)
In-Reply-To: <20230411-darling-chump-faaf8dec29ef@wendy>
On 2023/4/11 17:06, Conor Dooley wrote:
> Hey Mason,
>
> On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote:
>> Add the operating-points-v2 to support cpu scaling
>> on StarFive JH7110 SoC.
>
> (btw, there's no need to wrap commit messages at 52 columns, you have
> 72 to work with)
>
Hi Conor,
Thanks for your review.
Will place it in the same line.
>> It supports up to 4 cpu frequency loads.
>>
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 25 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 25 +++++++++++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index df582bddae4b..ae446b268e78 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -228,3 +228,28 @@ &uart0 {
>> pinctrl-0 = <&uart0_pins>;
>> status = "okay";
>> };
>> +
>> +&U74_1 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_2 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_3 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>> +
>> +&U74_4 {
>> + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
> ^^
> There's a double space in each of these.
>
>> + clock-names = "cpu";
>> + cpu-supply = <®_dcdc2>;
>> +};
>
> How come these two clock properties are being added in <board>.dtsi?
> Should they not be in <soc>.dtsi?
>> Thanks,
> Conor.
Yes, will move them to <soc>.dtsi
Thanks
Mason
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next prev parent reply other threads:[~2023-04-12 2:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 8:32 [PATCH v1 0/3] Add JH7110 cpufreq support Mason Huo
2023-04-11 8:32 ` [PATCH v1 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Mason Huo
2023-04-11 9:13 ` Conor Dooley
2023-04-11 14:49 ` Shengyu Qu
2023-04-12 2:36 ` Mason Huo
2023-04-12 2:36 ` Mason Huo
2023-04-11 8:32 ` [PATCH v1 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Mason Huo
2023-04-11 9:20 ` Conor Dooley
2023-04-12 2:36 ` Mason Huo
2023-04-11 8:32 ` [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Mason Huo
2023-04-11 9:06 ` Conor Dooley
2023-04-12 2:35 ` Mason Huo [this message]
2023-04-11 15:58 ` [PATCH v1 0/3] Add JH7110 cpufreq support Rafael J. Wysocki
2023-04-21 7:47 ` Viresh Kumar
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