Re: [PATCH v10 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core

From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
	Conor Dooley <conor.dooley@microchip.com>,
	 Geert Uytterhoeven <geert+renesas@glider.be>,
	Guo Ren <guoren@kernel.org>,
	 Andrew Jones <ajones@ventanamicro.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Samuel Holland <samuel@sholland.org>,
	linux-riscv@lists.infradead.org,
	 Christoph Hellwig <hch@infradead.org>,
	Rob Herring <robh+dt@kernel.org>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	 Biju Das <biju.das.jz@bp.renesas.com>,
	 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v10 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
Date: Mon, 31 Jul 2023 12:26:58 +0100	[thread overview]
Message-ID: <CA+V-a8t=R1EoEei_q6S9nsTyo9wNZwuvMOcCOJhrWPbG=XDxZg@mail.gmail.com> (raw)
In-Reply-To: <CAJM55Z_ZoKY5A6icpkZo+U5JQ5rMfNmCWz35EJ9RrH7bEgv53g@mail.gmail.com>

Hi Emil,

Thank you for the review.

On Mon, Jul 31, 2023 at 9:53 AM Emil Renner Berthing
<emil.renner.berthing@canonical.com> wrote:
>
> On Sun, 2 Jul 2023 at 22:37, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > I/O Coherence Port (IOCP) provides an AXI interface for connecting
> > external non-caching masters, such as DMA controllers. The accesses
> > from IOCP are coherent with D-Caches and L2 Cache.
> >
> > IOCP is a specification option and is disabled on the Renesas RZ/Five
> > SoC due to this reason IP blocks using DMA will fail.
> >
> > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
> > block that allows dynamic adjustment of memory attributes in the runtime.
> > It contains a configurable amount of PMA entries implemented as CSR
> > registers to control the attributes of memory locations in interest.
> > Below are the memory attributes supported:
> > * Device, Non-bufferable
> > * Device, bufferable
> > * Memory, Non-cacheable, Non-bufferable
> > * Memory, Non-cacheable, Bufferable
> > * Memory, Write-back, No-allocate
> > * Memory, Write-back, Read-allocate
> > * Memory, Write-back, Write-allocate
> > * Memory, Write-back, Read and Write-allocate
> >
> > More info about PMA (section 10.3):
> > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> >
> > As a workaround for SoCs with IOCP disabled CMO needs to be handled by
> > software. Firstly OpenSBI configures the memory region as
> > "Memory, Non-cacheable, Bufferable" and passes this region as a global
> > shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
> > allocations happen from this region and synchronization callbacks are
> > implemented to synchronize when doing DMA transactions.
> >
<snip>
> > +static const struct riscv_cache_ops ax45mp_cmo_ops = {
> > +       .wback = &ax45mp_dma_cache_wback,
> > +       .inv = &ax45mp_dma_cache_inv,
> > +       .wback_inv = &ax45mp_dma_cache_wback_inv,
> > +};
>
> Hi Prabhakar,
>
> If you're respinning this patchset anyway, I think you can mark this
> struct as __initdata since it's only used by
> riscv_noncoherent_register_cache_ops which copies the contents.
>
Agreed, I will update it in the next version.

Cheers,
Prabhakar

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