Re: [PATCH] riscv: Using CSR numbers to access CSRs

[Anup Patel <anup@brainfault.org>]

On Thu, Jul 11, 2019 at 1:19 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Since commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"),
> we should prefer accessing CSRs using their CSR numbers, but there
> are several leftovers like sstatus / sptbr we missed.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/riscv/kernel/entry.S |  6 +++---
>  arch/riscv/kernel/fpu.S   |  8 ++++----
>  arch/riscv/kernel/head.S  |  2 +-
>  arch/riscv/lib/uaccess.S  | 12 ++++++------
>  arch/riscv/mm/context.c   |  7 +------
>  5 files changed, 15 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index bc7a56e..74ccfd4 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -167,7 +167,7 @@ ENTRY(handle_exception)
>         tail do_IRQ
>  1:
>         /* Exceptions run with interrupts enabled */
> -       csrs sstatus, SR_SIE
> +       csrs CSR_SSTATUS, SR_SIE
>
>         /* Handle syscalls */
>         li t0, EXC_SYSCALL
> @@ -222,7 +222,7 @@ ret_from_syscall:
>
>  ret_from_exception:
>         REG_L s0, PT_SSTATUS(sp)
> -       csrc sstatus, SR_SIE
> +       csrc CSR_SSTATUS, SR_SIE
>         andi s0, s0, SR_SPP
>         bnez s0, resume_kernel
>
> @@ -265,7 +265,7 @@ work_pending:
>         bnez s1, work_resched
>  work_notifysig:
>         /* Handle pending signals and notify-resume requests */
> -       csrs sstatus, SR_SIE /* Enable interrupts for do_notify_resume() */
> +       csrs CSR_SSTATUS, SR_SIE /* Enable interrupts for do_notify_resume() */
>         move a0, sp /* pt_regs */
>         move a1, s0 /* current_thread_info->flags */
>         tail do_notify_resume
> diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S
> index 1defb06..631d315 100644
> --- a/arch/riscv/kernel/fpu.S
> +++ b/arch/riscv/kernel/fpu.S
> @@ -23,7 +23,7 @@ ENTRY(__fstate_save)
>         li  a2,  TASK_THREAD_F0
>         add a0, a0, a2
>         li t1, SR_FS
> -       csrs sstatus, t1
> +       csrs CSR_SSTATUS, t1
>         frcsr t0
>         fsd f0,  TASK_THREAD_F0_F0(a0)
>         fsd f1,  TASK_THREAD_F1_F0(a0)
> @@ -58,7 +58,7 @@ ENTRY(__fstate_save)
>         fsd f30, TASK_THREAD_F30_F0(a0)
>         fsd f31, TASK_THREAD_F31_F0(a0)
>         sw t0, TASK_THREAD_FCSR_F0(a0)
> -       csrc sstatus, t1
> +       csrc CSR_SSTATUS, t1
>         ret
>  ENDPROC(__fstate_save)
>
> @@ -67,7 +67,7 @@ ENTRY(__fstate_restore)
>         add a0, a0, a2
>         li t1, SR_FS
>         lw t0, TASK_THREAD_FCSR_F0(a0)
> -       csrs sstatus, t1
> +       csrs CSR_SSTATUS, t1
>         fld f0,  TASK_THREAD_F0_F0(a0)
>         fld f1,  TASK_THREAD_F1_F0(a0)
>         fld f2,  TASK_THREAD_F2_F0(a0)
> @@ -101,6 +101,6 @@ ENTRY(__fstate_restore)
>         fld f30, TASK_THREAD_F30_F0(a0)
>         fld f31, TASK_THREAD_F31_F0(a0)
>         fscsr t0
> -       csrc sstatus, t1
> +       csrc CSR_SSTATUS, t1
>         ret
>  ENDPROC(__fstate_restore)
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4e46f31..95010d7 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -29,7 +29,7 @@ ENTRY(_start)
>          * floating point in kernel space
>          */
>         li t0, SR_FS
> -       csrc sstatus, t0
> +       csrc CSR_SSTATUS, t0
>
>         /* Pick one hart to run the main boot sequence */
>         la a3, hart_lottery
> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
> index 399e6f0..ed2696c 100644
> --- a/arch/riscv/lib/uaccess.S
> +++ b/arch/riscv/lib/uaccess.S
> @@ -18,7 +18,7 @@ ENTRY(__asm_copy_from_user)
>
>         /* Enable access to user memory */
>         li t6, SR_SUM
> -       csrs sstatus, t6
> +       csrs CSR_SSTATUS, t6
>
>         add a3, a1, a2
>         /* Use word-oriented copy only if low-order bits match */
> @@ -47,7 +47,7 @@ ENTRY(__asm_copy_from_user)
>
>  3:
>         /* Disable access to user memory */
> -       csrc sstatus, t6
> +       csrc CSR_SSTATUS, t6
>         li a0, 0
>         ret
>  4: /* Edge case: unalignment */
> @@ -72,7 +72,7 @@ ENTRY(__clear_user)
>
>         /* Enable access to user memory */
>         li t6, SR_SUM
> -       csrs sstatus, t6
> +       csrs CSR_SSTATUS, t6
>
>         add a3, a0, a1
>         addi t0, a0, SZREG-1
> @@ -94,7 +94,7 @@ ENTRY(__clear_user)
>
>  3:
>         /* Disable access to user memory */
> -       csrc sstatus, t6
> +       csrc CSR_SSTATUS, t6
>         li a0, 0
>         ret
>  4: /* Edge case: unalignment */
> @@ -114,11 +114,11 @@ ENDPROC(__clear_user)
>         /* Fixup code for __copy_user(10) and __clear_user(11) */
>  10:
>         /* Disable access to user memory */
> -       csrs sstatus, t6
> +       csrs CSR_SSTATUS, t6
>         mv a0, a2
>         ret
>  11:
> -       csrs sstatus, t6
> +       csrs CSR_SSTATUS, t6
>         mv a0, a1
>         ret
>         .previous
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index 89ceb3c..beeb5d7 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -57,12 +57,7 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
>         cpumask_clear_cpu(cpu, mm_cpumask(prev));
>         cpumask_set_cpu(cpu, mm_cpumask(next));
>
> -       /*
> -        * Use the old spbtr name instead of using the current satp
> -        * name to support binutils 2.29 which doesn't know about the
> -        * privileged ISA 1.10 yet.
> -        */
> -       csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE);
> +       csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE);
>         local_flush_tlb_all();
>
>         flush_icache_deferred(next);
> --
> 2.7.4
>
>
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Thanks for this cleanup.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

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