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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0J627pM80T7+XlutPkaKlOVr/z1gAAVKrENSM8VXItA=; b=CtprZ5SXIqqvb22E0ZWmNHjEUCdnIoTQaQ8VhtsWcPXduf0fRkUWQ2N8sxNtiZBVN6 UsMXHTFcOv7v7mccRCQzqDsu5DsLIT8PeVDtwqXKr6pMbzmgbSZqBbu39ASNPy5oZp6d fIi6LLUjq2ehqR3H/I93V4QLlf3+vjgvvjnbuqRrtFN5gmZ5wE2ZU6/a5i9DJT0EvU5i 5fnmK01WYxsDmdblImbx1MRw+ahrHTaLbjP+20AmQW9FoCmpn8Z8Way4VwcsmQCsIsru AnPM8VyiJVZd0C++rT1rmrPJjGpqge0sZ+IJSo5YhuUYzhwoqWiNnwKugMnR8xcVHK7R iqDg== X-Gm-Message-State: AOAM530MGYos38EzT1GxVtKKATjBrhJEaExwAhXVv/h1o0BchQFsVHBz Xi8YR+vdAXNzZerbfcJIJiA9CGELSg0K4o1DQSuYdQ== X-Google-Smtp-Source: ABdhPJynaPKpbU6Sa4qfZHuvA4C6P4PN6EGPDdcoeLrQHPieARti1aWDcQP+/gphRMVoWP2V8oJ4kkwKrU/hwUWo/t4= X-Received: by 2002:a1c:2d91:: with SMTP id t139mr3589796wmt.3.1595331593814; Tue, 21 Jul 2020 04:39:53 -0700 (PDT) MIME-Version: 1.0 References: <20200717075101.263332-1-anup.patel@wdc.com> <20200717075101.263332-5-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Tue, 21 Jul 2020 17:09:41 +0530 Message-ID: Subject: Re: [PATCH v4 4/4] dt-bindings: timer: Add CLINT bindings To: Atish Patra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200721_073955_874466_108E463F X-CRM114-Status: GOOD ( 24.28 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Daniel Lezcano , Emil Renner Berhing , Anup Patel , "linux-kernel@vger.kernel.org List" , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Palmer Dabbelt , Alistair Francis , Thomas Gleixner , linux-riscv , Albert Ou Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 21, 2020 at 6:45 AM Atish Patra wrote: > > On Fri, Jul 17, 2020 at 12:52 AM Anup Patel wrote: > > > > We add DT bindings documentation for CLINT device. > > > > Signed-off-by: Anup Patel > > Reviewed-by: Palmer Dabbelt > > Tested-by: Emil Renner Berhing > > --- > > .../bindings/timer/sifive,clint.yaml | 58 +++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml > > > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > new file mode 100644 > > index 000000000000..8ad115611860 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SiFive Core Local Interruptor > > + > > +maintainers: > > + - Palmer Dabbelt > > + - Anup Patel > > + > > +description: > > + SiFive (and other RISC-V) SOCs include an implementation of the SiFive > > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > > + interrupts. It directly connects to the timer and inter-processor interrupt > > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > > + interrupt controller is the parent interrupt controller for CLINT device. > > + The clock frequency of CLINT is specified via "timebase-frequency" DT > > + property of "/cpus" DT node. The "timebase-frequency" DT property is > > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > > + > > +properties: > > + compatible: > > + items: > > + - const: sifive,clint0 > > + - const: sifive,fu540-c000-clint > > + > > + description: > > + Should be "sifive,-clint" and "sifive,clint". > > + Supported compatible strings are - > > + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > > + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive > > + CLINT v0 IP block with no chip integration tweaks. > > + Please refer to sifive-blocks-ip-versioning.txt for details > > + > > As the DT binding suggests that the clint device should be named as "sifive,**", > I think we should change the DT property in kendryte dts as well. Okay, I will do it as a separate patch. > > > + reg: > > + maxItems: 1 > > + > > + interrupts-extended: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts-extended > > + > > +examples: > > + - | > > + clint@2000000 { > > + compatible = "sifive,clint0", "sifive,fu540-c000-clint"; > > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > > + &cpu2intc 3 &cpu2intc 7 > > + &cpu3intc 3 &cpu3intc 7 > > + &cpu4intc 3 &cpu4intc 7>; > > + reg = <0x2000000 0x4000000>; > > + }; > > +... > > -- > > 2.25.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > Otherwise, > > Reviewed-by: Atish Patra > > -- > Regards, > Atish Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv