From: Anup Patel <anup@brainfault.org>
To: Christoph Hellwig <hch@lst.de>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH 02/15] riscv: cleanup do_trap_break
Date: Fri, 18 Oct 2019 08:21:08 +0530 [thread overview]
Message-ID: <CAAhSdy27==MERM6H1dL4L_vndgSQcwyise=+_ER3kXHxEh9PYw@mail.gmail.com> (raw)
In-Reply-To: <20191017173743.5430-3-hch@lst.de>
On Thu, Oct 17, 2019 at 11:07 PM Christoph Hellwig <hch@lst.de> wrote:
>
> If we always compile the get_break_insn_length inline function we can
> remove the ifdefs and let dead code elimination take care of the warn
> branch that is now unreadable because the report_bug stub always
> returns BUG_TRAP_TYPE_BUG.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/riscv/kernel/traps.c | 26 ++++++--------------------
> 1 file changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 1ac75f7d0bff..10a17e545f43 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -111,7 +111,6 @@ DO_ERROR_INFO(do_trap_ecall_s,
> DO_ERROR_INFO(do_trap_ecall_m,
> SIGILL, ILL_ILLTRP, "environment call from M-mode");
>
> -#ifdef CONFIG_GENERIC_BUG
> static inline unsigned long get_break_insn_length(unsigned long pc)
> {
> bug_insn_t insn;
> @@ -120,28 +119,15 @@ static inline unsigned long get_break_insn_length(unsigned long pc)
> return 0;
> return (((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? 4UL : 2UL);
> }
> -#endif /* CONFIG_GENERIC_BUG */
>
> asmlinkage void do_trap_break(struct pt_regs *regs)
> {
> - if (user_mode(regs)) {
> - force_sig_fault(SIGTRAP, TRAP_BRKPT,
> - (void __user *)(regs->sepc));
> - return;
> - }
> -#ifdef CONFIG_GENERIC_BUG
> - {
> - enum bug_trap_type type;
> -
> - type = report_bug(regs->sepc, regs);
> - if (type == BUG_TRAP_TYPE_WARN) {
> - regs->sepc += get_break_insn_length(regs->sepc);
> - return;
> - }
> - }
> -#endif /* CONFIG_GENERIC_BUG */
> -
> - die(regs, "Kernel BUG");
> + if (user_mode(regs))
> + force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->sepc);
> + else if (report_bug(regs->sepc, regs) == BUG_TRAP_TYPE_WARN)
> + regs->sepc += get_break_insn_length(regs->sepc);
> + else
> + die(regs, "Kernel BUG");
> }
>
> #ifdef CONFIG_GENERIC_BUG
> --
> 2.20.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
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next prev parent reply other threads:[~2019-10-18 2:51 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 17:37 RISC-V nommu support v5 Christoph Hellwig
2019-10-17 17:37 ` [PATCH 01/15] riscv: cleanup <asm/bug.h> Christoph Hellwig
2019-10-18 2:50 ` Anup Patel
2019-10-23 22:04 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 02/15] riscv: cleanup do_trap_break Christoph Hellwig
2019-10-18 2:51 ` Anup Patel [this message]
2019-10-23 22:05 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 03/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-18 2:51 ` Anup Patel
2019-10-18 23:55 ` Paul Walmsley
2019-10-28 8:12 ` Christoph Hellwig
2019-10-17 17:37 ` [PATCH 04/15] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-10-18 2:52 ` Anup Patel
2019-10-17 17:37 ` [PATCH 05/15] riscv: poison SBI calls " Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 06/15] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-18 2:53 ` Anup Patel
2019-10-17 17:37 ` [PATCH 07/15] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-18 2:55 ` Anup Patel
2019-10-17 17:37 ` [PATCH 08/15] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-10-18 2:57 ` Anup Patel
2019-10-17 17:37 ` [PATCH 09/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-18 3:00 ` Anup Patel
2019-11-14 7:39 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 10/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-11-14 7:40 ` Paul Walmsley
2019-10-17 17:37 ` [PATCH 11/15] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-10-18 3:01 ` Anup Patel
2019-10-17 17:37 ` [PATCH 12/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-10-18 3:05 ` Anup Patel
2019-10-17 17:37 ` [PATCH 13/15] riscv: add nommu support Christoph Hellwig
2019-10-18 3:04 ` Anup Patel
2019-10-17 17:37 ` [PATCH 14/15] riscv: provide a flat image loader Christoph Hellwig
2019-10-18 3:06 ` Anup Patel
2019-10-17 17:37 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-18 3:06 ` Anup Patel
2019-10-18 3:08 ` RISC-V nommu support v5 Anup Patel
2019-10-18 3:29 ` Paul Walmsley
2019-10-18 15:25 ` Christoph Hellwig
2019-10-18 23:46 ` Paul Walmsley
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