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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jqfpvi3iYp3AoWQd6MSO7doKcVpn2TJcLUHhv2lCYnI=; b=Cq3ZdYmU/m4kbx224KTIVQG04VocO5UtXmdu9Emkb8+J0yzfKC3kn1sHpXMNsREHS+ Ca6+e7gO+DlhP9B6hB6BXV0GdSnvdLIB1KhhKPfe1SZZa/IxfkbWcFevcdpMsTXLrViW AvyAZqmHHPrUqkpfB2xTMbkJ3chChyAykG0S0mGQmCcXq+lhrTBHMrLY1fhvNFY/TuJz 2Eqy0263cFoLPbS40wXyvKs6jUUA39hwTDMiFu1DUJ2xtzJcoitdFzTXUSHc9v8sh3L6 2s+AGSCBApcMCLgmeGACYNJGuq/BQ3ESQHO60UBubu3vDB5SBEZ3wyLFA1mtI3fGZa3S i/Tg== X-Gm-Message-State: AOAM5337SlfLo3iE/MIANpqVCaHKsITqIe3ZqKp/dT5YCRQDMErV8BWc l4W2N22Y7v8Q1liDi2G30fi4+7XdjKQzy2+s5z95Ug== X-Google-Smtp-Source: ABdhPJwx1knjHefqrB+oeWQ3YcqzAY6RsgARQklwQOrsgV4BeAw50AB+MKIpRinxVhKDLYaH38jdH075e1ij93+pORY= X-Received: by 2002:adf:ff87:: with SMTP id j7mr9282883wrr.128.1593403776321; Sun, 28 Jun 2020 21:09:36 -0700 (PDT) MIME-Version: 1.0 References: <3de3a480517d167a3faae086aa8ab0c0c7141d99.1593397455.git.zong.li@sifive.com> In-Reply-To: <3de3a480517d167a3faae086aa8ab0c0c7141d99.1593397455.git.zong.li@sifive.com> From: Anup Patel Date: Mon, 29 Jun 2020 09:39:24 +0530 Message-ID: Subject: Re: [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU To: Zong Li X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Paul Walmsley Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote: > > Add device tree bindings for performance monitor unit. And it passes the > dt_binding_check verification. > > Signed-off-by: Zong Li > --- > .../devicetree/bindings/riscv/pmu.yaml | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/pmu.yaml b/Documentation/devicetree/bindings/riscv/pmu.yaml > new file mode 100644 > index 000000000000..f55ccbc6c685 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/pmu.yaml > @@ -0,0 +1,59 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V Performance Monitor Units > + > +maintainers: > + - Zong Li > + - Paul Walmsley > + - Palmer Dabbelt > + > +properties: > + compatible: > + items: > + - const: riscv,pmu > + > + riscv,width-base-cntr: > + description: The width of cycle and instret CSRs. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + riscv,width-event-cntr: > + description: The width of hpmcounter CSRs. > + $ref: /schemas/types.yaml#/definitions/uint32 The terms "base" and "event" is confusing because we only have counters with no interrupt associated with it. The RISC-V spec defines 3 counters and rest are all implementation specific counters. I suggest using the terms "spec counters" and "impl counters" instead of "base counters" and "event counters". Further, "riscv,width" properties are redundant because RISC-V spec clearly tells that counters are 64bit for both RV32 and RV64. > + > + riscv,n-event-cntr: > + description: The number of hpmcounter CSRs. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + riscv,hw-event-map: > + description: The mapping of generic hardware events. Default is no mapping. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + riscv,hw-cache-event-map: > + description: The mapping of generic hardware cache events. > + Default is no mapping. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > +required: > + - compatible > + - riscv,width-base-cntr > + - riscv,width-event-cntr > + - riscv,n-event-cntr > + > +additionalProperties: false > + > +examples: > + - | > + pmu { > + compatible = "riscv,pmu"; > + riscv,width-base-cntr = <64>; > + riscv,width-event-cntr = <40>; > + riscv,n-event-cntr = <2>; > + riscv,hw-event-map = <0x0 0x0 0x1 0x1 0x3 0x0202 0x4 0x4000>; > + riscv,hw-cache-event-map = <0x010201 0x0102 0x010204 0x0802>; > + }; > + > +... > -- > 2.27.0 > Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv