From: Guo Ren <guoren@kernel.org>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: palmer@rivosinc.com, paul.walmsley@sifive.com,
falcon@tinylab.org, bjorn@kernel.org,
conor.dooley@microchip.com, linux-arch@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH] riscv: Add HAVE_IOREMAP_PROT support
Date: Fri, 21 Jul 2023 20:06:53 -0400 [thread overview]
Message-ID: <CAJF2gTTBbHDr4yD=aeof_h1WM6b_CD-yJcs6R5g=jt4-NdAR8w@mail.gmail.com> (raw)
In-Reply-To: <bb296a8e-4f84-f45d-8f46-5acfa73022d9@ghiti.fr>
On Mon, Jul 17, 2023 at 5:07 AM Alexandre Ghiti <alex@ghiti.fr> wrote:
>
> Hi Guo,
>
> On 16/07/2023 17:20, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Add pte_pgprot macro, then riscv could have HAVE_IOREMAP_PROT,
> > which will enable generic_access_phys() code, it is useful for
> > debug, eg, gdb.
>
>
> I don't understand, we already have the generic ioremap_prot()
> implementation since we select GENERIC_IOREMAP: shouldn't
> HAVE_IOREMAP_PROT imply that we have our own implementation?
They are different! See arch/arm64/Kconfig, which selects all of them.
HAVE_IOREMAP_PROT would enable your drivers/char/mem.c
generic_access_phys of mmap_mem_ops.
It's a small function enabling.
>
> Thanks,
>
> Alex
>
>
> > Because generic_access_phys() would call ioremap_prot()->
> > pgprot_nx() to disable excutable attribute, add definition
> > of pgprot_nx() for riscv.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > .../features/vm/ioremap_prot/arch-support.txt | 2 +-
> > arch/riscv/Kconfig | 1 +
> > arch/riscv/include/asm/pgtable.h | 15 +++++++++++++++
> > 3 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt
> > index a24149e59d73..ea8c8a361455 100644
> > --- a/Documentation/features/vm/ioremap_prot/arch-support.txt
> > +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt
> > @@ -21,7 +21,7 @@
> > | openrisc: | TODO |
> > | parisc: | TODO |
> > | powerpc: | ok |
> > - | riscv: | TODO |
> > + | riscv: | ok |
> > | s390: | ok |
> > | sh: | ok |
> > | sparc: | TODO |
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 4c07b9189c86..15900fa20797 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -117,6 +117,7 @@ config RISCV
> > select HAVE_FUNCTION_ERROR_INJECTION
> > select HAVE_GCC_PLUGINS
> > select HAVE_GENERIC_VDSO if MMU && 64BIT
> > + select HAVE_IOREMAP_PROT
> > select HAVE_IRQ_TIME_ACCOUNTING
> > select HAVE_KPROBES if !XIP_KERNEL
> > select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index 75970ee2bda2..c9552a161f90 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -415,6 +415,11 @@ static inline pte_t pte_mkhuge(pte_t pte)
> > return pte;
> > }
> >
> > +static inline pgprot_t pte_pgprot(pte_t pte)
> > +{
> > + return __pgprot(pte_val(pte) & ~_PAGE_PFN_MASK);
> > +}
> > +
> > #ifdef CONFIG_NUMA_BALANCING
> > /*
> > * See the comment in include/asm-generic/pgtable.h
> > @@ -573,6 +578,16 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
> > return ptep_test_and_clear_young(vma, address, ptep);
> > }
> >
> > +#define pgprot_nx pgprot_nx
> > +static inline pgprot_t pgprot_nx(pgprot_t _prot)
> > +{
> > + unsigned long prot = pgprot_val(_prot);
> > +
> > + prot &= ~_PAGE_EXEC;
> > +
> > + return __pgprot(prot);
> > +}
> > +
> > #define pgprot_noncached pgprot_noncached
> > static inline pgprot_t pgprot_noncached(pgprot_t _prot)
> > {
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
prev parent reply other threads:[~2023-07-22 0:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-16 15:20 [PATCH] riscv: Add HAVE_IOREMAP_PROT support guoren
2023-07-17 9:07 ` Alexandre Ghiti
2023-07-22 0:06 ` Guo Ren [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAJF2gTTBbHDr4yD=aeof_h1WM6b_CD-yJcs6R5g=jt4-NdAR8w@mail.gmail.com' \
--to=guoren@kernel.org \
--cc=alex@ghiti.fr \
--cc=bjorn@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=falcon@tinylab.org \
--cc=guoren@linux.alibaba.com \
--cc=linux-arch@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).