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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZpBY/PhrvExkev45/pQ1Qu7CoJvNzyMndE/eWx97fMU=; b=MYz/zJ2g2l12gp93HvJ2H2Qif6jTtEBPgetEUDSrOsKhXUpXFIpEHg9/TawEwAGNx8 tqScfvj3M+ni8jxS+lyiqw2sA1Vo4ks/htKDcOXNRdpF8eJsM6B8DO4cIEodPwyIF/ZL Km8cQLf5egHjkGLGdKBwBvJNyYT+4NWdE77auIYN0+hW059RFMb38i/L5ul+UWtRJez6 sIdK5CQi3fFR9ysX7qqrSNTY3Hd7uPlUO6poASfonf3ZkqZJ0vFbN183KA3VAuOEaDxt S+5CaU80aPNFvEBs/nBkY1BSBj4sF/2cQSjv9zMCIE5ZJLbk69L55CU6uNN0ja6jLxp+ MarQ== X-Gm-Message-State: AOAM530maf0P9yKNV8JbLU4tajFVn79hnTgJAjythd5cVTkEP18RAbe1 2PuwhZ/Ta2l/MHhwQXDuZphNs+HqlA+5APOQNpNFeT7pDdg3TA== X-Google-Smtp-Source: ABdhPJwTf94VErmAjkPpNTDsEVcqGB2LVv1W5/dNVrcWEhT6lWcsdaSCiTlXRXIqMBcHLL8+1//OEb+4eT3sY5Uz5SQ= X-Received: by 2002:aca:1c05:: with SMTP id c5mr10429190oic.32.1593409946707; Sun, 28 Jun 2020 22:52:26 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Zong Li Date: Mon, 29 Jun 2020 13:52:15 +0800 Message-ID: Subject: Re: [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V To: Anup Patel , alankao@andestech.com X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Paul Walmsley Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 29, 2020 at 12:53 PM Anup Patel wrote: > > On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote: > > > > This patch set adds raw event support on RISC-V. In addition, we > > introduce the DT mechanism to make our perf more generic and common. > > > > Currently, we set the hardware events by writing the mhpmeventN CSRs, it > > would raise an illegal instruction exception and trap into m-mode to > > emulate event selector CSRs access. It doesn't make sense because we > > shouldn't write the m-mode CSRs in s-mode. Ideally, we should set event > > selector through standard SBI call or the shadow CSRs of s-mode. We have > > prepared a proposal of a new SBI extension, called "PMU SBI extension", > > but we also discussing the feasibility of accessing these PMU CSRs on > > s-mode at the same time, such as delegation mechanism, so I was > > wondering if we could use SBI calls first and make the PMU SBI extension > > as legacy when s-mode access mechanism is accepted by Foundation? or > > keep the current situation to see what would happen in the future. > > > > This patch set also introduces the DT mechanism, we don't want to add too > > much platform-dependency code in perf like other architectures, so we > > put the mapping of generic hardware events to DT, then we can easy to > > transfer generic hardware events to vendor's own hardware events without > > any platfrom-dependency stuff in our perf. > > Please re-write this series to have RISC-V PMU driver as a regular > platform driver as drivers/perf/riscv_pmu.c. > > The PMU related sources will have to be removed from arch/riscv. > > Based on implementation of final drivers/perf/riscv_pmu.c we will > come-up with drivers/perf/riscv_sbi_pmu.c driver for SBI perf counters. > There are some different ways to implement perf, and current implementation seems to be consensus when perf was introduced at the beginning [0][1]. I don't persist to which one, I could change the implementation as you mentioned if it is a new consensus one. [0] https://github.com/riscv/riscv-linux/pull/124#issuecomment-367563910 [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/f19TmCNP6yA > Regards, > Anup > > > > > Zong Li (6): > > dt-bindings: riscv: Add YAML documentation for PMU > > riscv: dts: sifive: Add DT support for PMU > > riscv: add definition of hpmcounter CSRs > > riscv: perf: Add raw event support > > riscv: perf: introduce DT mechanism > > riscv: remove PMU menu of Kconfig > > > > .../devicetree/bindings/riscv/pmu.yaml | 59 +++ > > arch/riscv/Kconfig | 13 - > > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 13 + > > arch/riscv/include/asm/csr.h | 58 +++ > > arch/riscv/include/asm/perf_event.h | 100 ++-- > > arch/riscv/kernel/Makefile | 2 +- > > arch/riscv/kernel/perf_event.c | 471 +++++++++++------- > > 7 files changed, 471 insertions(+), 245 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml > > > > -- > > 2.27.0 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv