From: Zong Li <zong.li@sifive.com>
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>,
Anup Patel <apatel@ventanamicro.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Greentime Hu <greentime.hu@sifive.com>,
linux@rivosinc.com,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Sebastien Boeuf <seb@rivosinc.com>,
iommu@lists.linux.dev, Nick Kossifidis <mick@ics.forth.gr>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 00/13] Linux RISC-V IOMMU Support
Date: Wed, 10 Apr 2024 13:38:18 +0800 [thread overview]
Message-ID: <CANXhq0q0UakMSBQ=j0K21TpC-Hq8eX4BrFQ0K6XzQ=h1Pr_buA@mail.gmail.com> (raw)
In-Reply-To: <CAH2o1u6seMkt5stxkpr4JCdmU3ZXDid5gDL7+9abNg=zPqdFdQ@mail.gmail.com>
On Fri, Apr 5, 2024 at 1:37 AM Tomasz Jeznach <tjeznach@rivosinc.com> wrote:
>
> On Fri, Feb 23, 2024 at 6:04 AM Zong Li <zong.li@sifive.com> wrote:
> >
> > >
> > > The RISC-V IOMMU specification is now ratified as-per the RISC-V international
> > > process [1]. The latest frozen specifcation can be found at:
> > > https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
> > >
> > > At a high-level, the RISC-V IOMMU specification defines:
> > > 1) Memory-mapped programming interface
> > > - Mandatory and optional registers layout and description.
> > > - Software guidelines for device initialization and capabilities discovery.
> > > 2) In-memory queue interface
> > > - A command-queue used by software to queue commands to the IOMMU.
> > > - A fault/event queue used to bring faults and events to software’s attention.
> > > - A page-request queue used to report “Page Request” messages received from
> > > PCIe devices.
> > > - Message-signalled and wire-signaled interrupt mechanism.
> > > 3) In-memory data structures
> > > - Device-context: used to associate a device with an address space and to hold
> > > other per-device parameters used by the IOMMU to perform address translations.
> > > - Process-contexts: used to associate a different virtual address space based on
> > > device provided process identification number.
> > > - MSI page table configuration used to direct an MSI to a guest interrupt file
> > > in an IMSIC. The MSI page table formats are defined by the Advanced Interrupt
> > > Architecture specification [2].
> > >
> > > This series introduces complete single-level translation support, including shared
> > > virtual address (SVA), ATS/PRI interfaces in the kernel driver. Patches adding MSI
> > > identity remapping and G-Stage translation (GPA to SPA) are added only to excercise
> > > hardware interfaces, to be complemented with AIA/KVM bindings in follow-up series.
> > >
> > > This series is a logical regrouping of series of incremental patches based on
> > > RISC-V International IOMMU Task Group discussions and specification development
> > > process. Original series can be found at the maintainer's repository branch [3].
> > >
> > > These patches can also be found in the riscv_iommu_v1 branch at:
> > > https://github.com/tjeznach/linux/tree/riscv_iommu_v1
> > >
> > > To test this series, use QEMU/OpenSBI with RISC-V IOMMU implementation available in
> > > the riscv_iommu_v1 branch at:
> > > https://github.com/tjeznach/qemu/tree/riscv_iommu_v1
> > >
> > > References:
> > > [1] - https://wiki.riscv.org/display/HOME/Specification+Status
> > > [2] - https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
> > > [3] - https://github.com/tjeznach/qemu/tree/tjeznach/riscv-iommu-20230719
> > >
> > >
> > > Anup Patel (1):
> > > dt-bindings: Add RISC-V IOMMU bindings
> > >
> > > Tomasz Jeznach (10):
> > > RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support.
> > > RISC-V: arch/riscv/config: enable RISC-V IOMMU support
> > > MAINTAINERS: Add myself for RISC-V IOMMU driver
> > > RISC-V: drivers/iommu/riscv: Add sysfs interface
> > > RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues
> > > RISC-V: drivers/iommu/riscv: Add device context support
> > > RISC-V: drivers/iommu/riscv: Add page table support
> > > RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support.
> > > RISC-V: drivers/iommu/riscv: Add MSI identity remapping
> > > RISC-V: drivers/iommu/riscv: Add G-Stage translation support
> > >
> > > .../bindings/iommu/riscv,iommu.yaml | 146 ++
> > > MAINTAINERS | 7 +
> > > arch/riscv/configs/defconfig | 1 +
> > > drivers/iommu/Kconfig | 1 +
> > > drivers/iommu/Makefile | 2 +-
> > > drivers/iommu/io-pgtable.c | 3 +
> > > drivers/iommu/riscv/Kconfig | 22 +
> > > drivers/iommu/riscv/Makefile | 1 +
> > > drivers/iommu/riscv/io_pgtable.c | 266 ++
> > > drivers/iommu/riscv/iommu-bits.h | 704 ++++++
> > > drivers/iommu/riscv/iommu-pci.c | 206 ++
> > > drivers/iommu/riscv/iommu-platform.c | 160 ++
> > > drivers/iommu/riscv/iommu-sysfs.c | 183 ++
> > > drivers/iommu/riscv/iommu.c | 2130 +++++++++++++++++
> > > drivers/iommu/riscv/iommu.h | 165 ++
> > > include/linux/io-pgtable.h | 2 +
> > > 16 files changed, 3998 insertions(+), 1 deletion(-)
> > > create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> > > create mode 100644 drivers/iommu/riscv/Kconfig
> > > create mode 100644 drivers/iommu/riscv/Makefile
> > > create mode 100644 drivers/iommu/riscv/io_pgtable.c
> > > create mode 100644 drivers/iommu/riscv/iommu-bits.h
> > > create mode 100644 drivers/iommu/riscv/iommu-pci.c
> > > create mode 100644 drivers/iommu/riscv/iommu-platform.c
> > > create mode 100644 drivers/iommu/riscv/iommu-sysfs.c
> > > create mode 100644 drivers/iommu/riscv/iommu.c
> > > create mode 100644 drivers/iommu/riscv/iommu.h
> > >
> > > --
> > > 2.34.1
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> > Hi Tomasz,
> > Could I know if you have a plan for the next version and if you have
> > any estimates for when the v2 patch will be ready? We have some
> > patches based on top of your old implementation, and it would be great
> > if we can rebase them onto your next version. Thanks.
>
> Hi Zong,
>
> Thank you for your interest. Next version of the iommu/riscv is almost ready to
> be sent in next few days.
Hi Tomasz,
Thanks you for the update, I would help to review the v2 series as well.
> There is a number of bug fixes and design changes based on the testing and
> great feedback after v1 was published.
> Upcoming patch set will be smaller, with core functionality only, hopefully to
> make the review easier. Functionality related to the MSI remapping, shared
> virtual addressing, nested translations will be moved to separate patch sets.
>
> Complete, up to date revision is always available at
> https://github.com/tjeznach/linux/
>
> regards,
> - Tomasz
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
prev parent reply other threads:[~2024-04-10 5:38 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 19:33 [PATCH 00/13] Linux RISC-V IOMMU Support Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 01/11] RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support Tomasz Jeznach
2023-07-19 20:49 ` Conor Dooley
2023-07-19 21:43 ` Tomasz Jeznach
2023-07-20 19:27 ` Conor Dooley
2023-07-21 9:44 ` Conor Dooley
2023-07-20 10:38 ` Baolu Lu
2023-07-20 12:31 ` Baolu Lu
2023-07-20 17:30 ` Tomasz Jeznach
2023-07-28 2:42 ` Zong Li
2023-08-02 20:15 ` Tomasz Jeznach
2023-08-02 20:25 ` Conor Dooley
2023-08-03 3:37 ` Zong Li
2023-08-03 0:18 ` Jason Gunthorpe
2023-08-03 8:27 ` Zong Li
2023-08-16 18:05 ` Robin Murphy
2024-04-13 10:15 ` Xingyou Chen
2023-07-19 19:33 ` [PATCH 02/11] RISC-V: arch/riscv/config: enable RISC-V IOMMU support Tomasz Jeznach
2023-07-19 20:22 ` Conor Dooley
2023-07-19 21:07 ` Tomasz Jeznach
2023-07-20 6:37 ` Krzysztof Kozlowski
2023-07-19 19:33 ` [PATCH 03/11] dt-bindings: Add RISC-V IOMMU bindings Tomasz Jeznach
2023-07-19 20:19 ` Conor Dooley
[not found] ` <CAH2o1u6CZSb7pXcaXmh7dJQmNZYh3uORk4x7vJPrb+uCwFdU5g@mail.gmail.com>
2023-07-19 20:57 ` Conor Dooley
2023-07-19 21:37 ` Rob Herring
2023-07-19 23:04 ` Tomasz Jeznach
2023-07-24 8:03 ` Zong Li
2023-07-24 10:02 ` Anup Patel
2023-07-24 11:31 ` Zong Li
2023-07-24 12:10 ` Anup Patel
2023-07-24 13:23 ` Zong Li
2023-07-26 3:21 ` Baolu Lu
2023-07-26 4:26 ` Zong Li
2023-07-26 12:17 ` Jason Gunthorpe
2023-07-27 2:42 ` Zong Li
2023-08-09 14:57 ` Jason Gunthorpe
2023-08-15 1:28 ` Zong Li
2023-08-15 18:38 ` Jason Gunthorpe
2023-08-16 2:16 ` Zong Li
2023-08-16 4:10 ` Baolu Lu
2023-07-19 19:33 ` [PATCH 04/11] MAINTAINERS: Add myself for RISC-V IOMMU driver Tomasz Jeznach
2023-07-20 12:42 ` Baolu Lu
2023-07-20 17:32 ` Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 05/11] RISC-V: drivers/iommu/riscv: Add sysfs interface Tomasz Jeznach
2023-07-20 6:38 ` Krzysztof Kozlowski
2023-07-20 18:30 ` Tomasz Jeznach
2023-07-20 21:37 ` Krzysztof Kozlowski
2023-07-20 22:08 ` Conor Dooley
2023-07-21 3:49 ` Tomasz Jeznach
2023-07-20 12:50 ` Baolu Lu
2023-07-20 17:47 ` Tomasz Jeznach
2023-07-19 19:33 ` [PATCH 06/11] RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues Tomasz Jeznach
2023-07-20 3:11 ` Nick Kossifidis
2023-07-20 18:00 ` Tomasz Jeznach
2023-07-20 18:43 ` Conor Dooley
2023-07-24 9:47 ` Zong Li
2023-07-28 5:18 ` Tomasz Jeznach
2023-07-28 8:48 ` Zong Li
2023-07-20 13:08 ` Baolu Lu
2023-07-20 17:49 ` Tomasz Jeznach
2023-07-29 12:58 ` Zong Li
2023-07-31 9:32 ` Nick Kossifidis
2023-07-31 13:15 ` Zong Li
2023-07-31 23:35 ` Nick Kossifidis
2023-08-01 0:37 ` Zong Li
2023-08-02 20:28 ` Tomasz Jeznach
2023-08-02 20:50 ` Tomasz Jeznach
2023-08-03 8:24 ` Zong Li
2023-08-16 18:49 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 07/11] RISC-V: drivers/iommu/riscv: Add device context support Tomasz Jeznach
2023-08-16 19:08 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 08/11] RISC-V: drivers/iommu/riscv: Add page table support Tomasz Jeznach
2023-07-25 13:13 ` Zong Li
2023-07-31 7:19 ` Zong Li
2023-08-16 21:04 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 09/11] RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support Tomasz Jeznach
2023-07-31 9:04 ` Zong Li
2023-07-19 19:33 ` [PATCH 10/11] RISC-V: drivers/iommu/riscv: Add MSI identity remapping Tomasz Jeznach
2023-07-31 8:02 ` Zong Li
2023-08-16 21:43 ` Robin Murphy
2023-07-19 19:33 ` [PATCH 11/11] RISC-V: drivers/iommu/riscv: Add G-Stage translation support Tomasz Jeznach
2023-07-31 8:12 ` Zong Li
2023-08-16 21:13 ` Robin Murphy
[not found] ` <CAHCEehJKYu3-GSX2L6L4_VVvYt1MagRgPJvYTbqekrjPw3ZSkA@mail.gmail.com>
2024-02-23 14:04 ` [PATCH 00/13] Linux RISC-V IOMMU Support Zong Li
2024-04-04 17:37 ` Tomasz Jeznach
2024-04-10 5:38 ` Zong Li [this message]
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