From: Biju Das <biju.das.jz@bp.renesas.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
Date: Wed, 27 Jul 2022 12:56:28 +0000 [thread overview]
Message-ID: <OS0PR01MB5922FDF8CFFE44A611D3783886979@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <80f08089-e3bb-983e-313b-45613364829e@linaro.org>
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: 27 July 2022 13:37
> To: Biju Das <biju.das.jz@bp.renesas.com>; Lad, Prabhakar
> <prabhakar.csengg@gmail.com>
> Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>;
> Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Albert
> Ou <aou@eecs.berkeley.edu>; Anup Patel <anup@brainfault.org>; Linux-
> Renesas <linux-renesas-soc@vger.kernel.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-riscv
> <linux-riscv@lists.infradead.org>; LKML <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>
> On 27/07/2022 14:21, Biju Das wrote:
> > Hi,
> >
> >> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> >> documentation for Renesas RZ/Five SoC and SMARC EVK
> >>
> >> On 27/07/2022 13:37, Lad, Prabhakar wrote:
> >>>>>>
> >>>>> I did run the dtbs_check test as per your suggestion (below is the
> >>>>> log) and didn't see "no matching schema error"
> >>>>>
> >>>>
> >>>> So you do not see any errors at all. Then it does not work, does
> it?
> >>>>
> >>> Right I reverted my changes I can see it complaining, dtb_check
> >>> seems to have returned false positive in my case.
> >>>
> >>> What approach would you suggest to ignore the schema here?
> >>
> >> I don't think currently it would work with your approach. Instead,
> >> you should select here all SoCs which the schema should match.
> >>
> >> This leads to my previous concern - you use the same SoC compatible
> >> for two different architectures and different SoCs: ARMv8 and RISC-V.
> >
> > Or is it same SoC(R9A07G043) based on two different CPU architectures
> > (ARMv8 and RISC-V)
>
> Then it is not the same SoC! Same means same, identical. CPU
> architecture is one of the major differences, which means it is not the
> same.
Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
differences for SoC based on ARMV8 and RISC-V which has separate compatible like
r9a07g043u11 and r9a07g043f01?
>
> > Using same SoM and Carrier board?
>
> It's like saying PC with x86 and ARMv8 board are the same because they
> both use same "PC chassis".
What I meant is board based on Family SoC(R9A07G043) that is either based on ARMv8 or
RISC-V cpu architecture.
Cheers,
Biju
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next prev parent reply other threads:[~2022-07-27 12:56 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:48 ` Lad, Prabhakar
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 23:37 ` Lad, Prabhakar
2022-07-27 15:43 ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:27 ` Biju Das
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:09 ` Krzysztof Kozlowski
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Biju Das
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:56 ` Biju Das [this message]
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 15:32 ` Lad, Prabhakar
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 15:10 ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:49 ` Conor.Dooley
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-27 8:00 ` Lad, Prabhakar
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