From: Jisheng Zhang <jszhang@kernel.org>
To: Zhangjin Wu <falcon@tinylab.org>
Cc: palmer@rivosinc.com, conor@kernel.org, guoren@kernel.org,
linux-riscv@lists.infradead.org, npiggin@gmail.com,
paul.walmsley@sifive.com, paulburton@kernel.org,
vincent.chen@sifive.com, tim.bird@sony.com
Subject: Re: [PATCH v3] RISC-V: Enable dead code elimination
Date: Sun, 21 May 2023 17:08:31 +0800 [thread overview]
Message-ID: <ZGnfj6GIcam6O0ay@xhacker> (raw)
In-Reply-To: <ZGnbfhpLUY7w9Sdu@xhacker>
On Sun, May 21, 2023 at 04:51:14PM +0800, Jisheng Zhang wrote:
> On Sun, May 21, 2023 at 04:48:47PM +0800, Jisheng Zhang wrote:
> > On Wed, May 17, 2023 at 04:29:36PM +0800, Zhangjin Wu wrote:
> > > Select CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION for RISC-V, allowing
> > > the user to enable dead code elimination. In order for this to work,
> > > ensure that we keep the alternative table by annotating them with KEEP.
> > >
> > > This boots well on qemu with both rv32_defconfig & rv64 defconfig, but
> > > it only shrinks their builds by ~1%, a smaller config is thereforce
> > > customized to test this feature:
> >
> > OOPS, I didn't noticed that you have sent out the patch and you are now
> > in v3. I may read your patch sevral months ago, but I forget it.
> > But your version missed an important preparation patch which is
> > to fix the typo in commom vmlinux.lds.h in asm-generic, thus LD_ORPHAN_WARN
> > will warn loudly. See[1] for more details.
> >
> > Another missing point is we need to keep the .init.pi* and .init.bss*
> > sections. See[1] for more details.
> >
> > Since you are the first person to send out the patch of
> > HAVE_LD_DEAD_CODE_DATA_ELIMINATION for riscv, do you mind if I update
> > my series and take your patch in my series v2, make you as the commmit
> > author, use your commit msg, and add my co-developped tag etc?
Another option is: I remove patch4 from my series and you send out an
updated version to fix the missing .init.pi* and .init.bss* KEEP.
>
> forget to add Link reference:
>
> [1] Link: https://lore.kernel.org/linux-riscv/20230511141211.2418-1-jszhang@kernel.org/
>
> >
> > Thanks
> >
> > >
> > > | rv32 | rv64
> > > --------|------------------------|---------------------
> > > No DCE | 4460684 | 4893488
> > > DCE | 3986716 | 4376400
> > > Shrink | 473968 (~10.6%) | 517088 (~10.5%)
> > >
> > > The config used above only reserves necessary options to boot on qemu
> > > with serial console, more like the size-critical embedded scenes:
> > >
> > > - rv64 config: https://pastebin.com/crz82T0s
> > > - rv32 config: rv64 config + 32-bit.config
> > >
> > > Signed-off-by: Zhangjin Wu <falcon@tinylab.org>
> > > ---
> > > arch/riscv/Kconfig | 1 +
> > > arch/riscv/kernel/vmlinux.lds.S | 2 +-
> > > 2 files changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > > index 348c0fa1fc8c..d2eb1a862ea8 100644
> > > --- a/arch/riscv/Kconfig
> > > +++ b/arch/riscv/Kconfig
> > > @@ -111,6 +111,7 @@ config RISCV
> > > select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL
> > > select HAVE_KRETPROBES if !XIP_KERNEL
> > > select HAVE_RETHOOK if !XIP_KERNEL
> > > + select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
> > > select HAVE_MOVE_PMD
> > > select HAVE_MOVE_PUD
> > > select HAVE_PCI
> > > diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
> > > index e5f9f4677bbf..0f5dfbc113d4 100644
> > > --- a/arch/riscv/kernel/vmlinux.lds.S
> > > +++ b/arch/riscv/kernel/vmlinux.lds.S
> > > @@ -112,7 +112,7 @@ SECTIONS
> > > . = ALIGN(8);
> > > .alternative : {
> > > __alt_start = .;
> > > - *(.alternative)
> > > + KEEP(*(.alternative))
> > > __alt_end = .;
> > > }
> > > __init_end = .;
> > > --
> > > 2.25.1
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2023-05-21 9:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 8:29 [PATCH v3] RISC-V: Enable dead code elimination Zhangjin Wu
2023-05-17 8:41 ` Zhangjin Wu
2023-05-21 2:23 ` guoren
2023-05-21 4:09 ` Bin Meng
2023-05-21 8:48 ` Jisheng Zhang
2023-05-21 8:51 ` Jisheng Zhang
2023-05-21 9:08 ` Jisheng Zhang [this message]
2023-05-21 12:41 ` Zhangjin Wu
2023-05-21 13:32 ` Conor Dooley
2023-05-21 14:56 ` Zhangjin Wu
2023-05-21 15:06 ` Conor Dooley
2023-06-20 20:13 ` Nick Desaulniers
2023-06-20 20:17 ` Palmer Dabbelt
2023-06-20 20:22 ` Conor Dooley
2023-06-20 20:26 ` Nick Desaulniers
2023-06-20 20:41 ` Palmer Dabbelt
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