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[73.95.159.87]) by smtp.gmail.com with ESMTPSA id q2sm13649895ita.0.2019.04.25.12.00.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Apr 2019 12:00:01 -0700 (PDT) Date: Thu, 25 Apr 2019 12:00:00 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig Subject: Re: [PATCH 1/9] riscv: use asm-generic/extable.h In-Reply-To: <20190411115623.5749-2-hch@lst.de> Message-ID: References: <20190411115623.5749-1-hch@lst.de> <20190411115623.5749-2-hch@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_120003_292700_F87AFFEC X-CRM114-Status: GOOD ( 12.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, Palmer Dabbelt Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, 11 Apr 2019, Christoph Hellwig wrote: > Signed-off-by: Christoph Hellwig Usually we'd nag about https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst#n102 Otherwise, Reviewed-by: Paul Walmsley - Paul > --- > arch/riscv/include/asm/Kbuild | 1 + > arch/riscv/include/asm/uaccess.h | 7 +------ > 2 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild > index cccd12cf27d4..5a7a19d9aa7f 100644 > --- a/arch/riscv/include/asm/Kbuild > +++ b/arch/riscv/include/asm/Kbuild > @@ -4,6 +4,7 @@ generic-y += compat.h > generic-y += cputime.h > generic-y += device.h > generic-y += div64.h > +generic-y += extable.h > generic-y += dma.h > generic-y += dma-contiguous.h > generic-y += dma-mapping.h > diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h > index fb53a8089e76..cc5b253d4c57 100644 > --- a/arch/riscv/include/asm/uaccess.h > +++ b/arch/riscv/include/asm/uaccess.h > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > #include > > #define __enable_user_access() \ > @@ -98,12 +99,6 @@ static inline int __access_ok(unsigned long addr, unsigned long size) > * on our cache or tlb entries. > */ > > -struct exception_table_entry { > - unsigned long insn, fixup; > -}; > - > -extern int fixup_exception(struct pt_regs *state); > - > #if defined(__LITTLE_ENDIAN) > #define __MSW 1 > #define __LSW 0 > -- > 2.20.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv