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From: Paul Walmsley <paul.walmsley@sifive.com>
To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Christoph Hellwig <hch@lst.de>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers
Date: Tue, 13 Aug 2019 10:44:02 -0700 (PDT)	[thread overview]
Message-ID: <alpine.DEB.2.21.9999.1908131032260.30024@viisi.sifive.com> (raw)
In-Reply-To: <20190813154747.24256-2-hch@lst.de>

Thomas, Jason, Marc,

On Tue, 13 Aug 2019, Christoph Hellwig wrote:

> When running in M-mode we still the S-mode plic handlers in the DT.
> Ignore them by setting the maximum threshold.
> 
> Signed-off-by: Christoph Hellwig <hch@lst.de>

If you're happy with this, could one of you ack it so we can merge it 
with the rest of this series through the RISC-V tree?

thanks

- Paul

> ---
>  drivers/irqchip/irq-sifive-plic.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index cf755964f2f8..c72c036aea76 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -244,6 +244,7 @@ static int __init plic_init(struct device_node *node,
>  		struct plic_handler *handler;
>  		irq_hw_number_t hwirq;
>  		int cpu, hartid;
> +		u32 threshold = 0;
>  
>  		if (of_irq_parse_one(node, i, &parent)) {
>  			pr_err("failed to parse parent for context %d.\n", i);
> @@ -266,10 +267,16 @@ static int __init plic_init(struct device_node *node,
>  			continue;
>  		}
>  
> +		/*
> +		 * When running in M-mode we need to ignore the S-mode handler.
> +		 * Here we assume it always comes later, but that might be a
> +		 * little fragile.
> +		 */
>  		handler = per_cpu_ptr(&plic_handlers, cpu);
>  		if (handler->present) {
>  			pr_warn("handler already present for context %d.\n", i);
> -			continue;
> +			threshold = 0xffffffff;
> +			goto done;
>  		}
>  
>  		handler->present = true;
> @@ -279,8 +286,9 @@ static int __init plic_init(struct device_node *node,
>  		handler->enable_base =
>  			plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
>  
> +done:
>  		/* priority must be > threshold to trigger an interrupt */
> -		writel(0, handler->hart_base + CONTEXT_THRESHOLD);
> +		writel(threshold, handler->hart_base + CONTEXT_THRESHOLD);
>  		for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
>  			plic_toggle(handler, hwirq, 0);
>  		nr_handlers++;
> -- 
> 2.20.1
> 
> 


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  reply	other threads:[~2019-08-13 17:44 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 17:44   ` Paul Walmsley [this message]
2019-08-14  9:06     ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 16:36   ` Paul Walmsley
2019-08-13 16:42     ` Christoph Hellwig
2019-08-13 16:51       ` Paul Walmsley
2019-08-13 19:44   ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-14  4:41   ` Paul Walmsley
2019-08-19 10:18     ` Christoph Hellwig
2019-09-01  8:03     ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 16:29   ` Mark Rutland
2019-08-19 10:16     ` Christoph Hellwig
2019-08-27 23:37       ` Palmer Dabbelt
2019-08-28  6:11         ` Christoph Hellwig
2019-09-03 18:48           ` Palmer Dabbelt
2019-09-04  2:05             ` Alan Kao
2019-08-21  0:24   ` Atish Patra
2019-08-21  0:42     ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-20 21:04   ` Atish Patra
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-20 21:05   ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-14  1:00   ` Alan Kao
2019-08-14  1:07     ` Alan Kao
2019-08-14  4:35     ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-20 21:07   ` Atish Patra
2019-08-21  4:14   ` Troy Benjegerdes
2019-08-21  7:12     ` Christoph Hellwig
2019-08-21 17:31     ` Atish Patra
2019-08-21 17:54       ` Troy Benjegerdes
2019-08-21 23:02         ` Anup Patel
2019-08-21 23:32           ` Troy Benjegerdes

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