From: Logan Gunthorpe <logang@deltatee.com>
To: Yash Shah <yash.shah@sifive.com>,
"Paul Walmsley ( Sifive)" <paul.walmsley@g.sifive.com>,
"Palmer Dabbelt ( Sifive)" <palmer@g.sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "sorear2@gmail.com" <sorear2@gmail.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"alex@ghiti.fr" <alex@ghiti.fr>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"Anup.Patel@wdc.com" <Anup.Patel@wdc.com>,
"rppt@linux.ibm.com" <rppt@linux.ibm.com>,
Sachin Ghadi <sachin.ghadi@sifive.com>,
Greentime Hu <greentime.hu@g.sifive.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"will@kernel.org" <will@kernel.org>,
"allison@lohutok.net" <allison@lohutok.net>
Subject: Re: [PATCH] RISC-V: Add PCIe I/O BAR memory mapping
Date: Thu, 24 Oct 2019 10:24:02 -0600 [thread overview]
Message-ID: <c4817ec1-4e50-5646-68f0-caeb0ab6f0bf@deltatee.com> (raw)
In-Reply-To: <1571908438-4802-1-git-send-email-yash.shah@sifive.com>
On 2019-10-24 3:14 a.m., Yash Shah wrote:
> For I/O BARs to work correctly on RISC-V Linux, we need to establish a
> reserved memory region for them, so that drivers that wish to use I/O BARs
> can issue reads and writes against a memory region that is mapped to the
> host PCIe controller's I/O BAR MMIO mapping.
I don't think other arches do this. ioremap() typically just uses
virtual address space in the VMALLOC region, PCI doesn't need it's own
range. As far as I know the ioremap() implementation in riscv already
does this.
In any case, 16MB for PCI bar space seems woefully inadequate.
Logan
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> arch/riscv/include/asm/io.h | 7 +++++++
> arch/riscv/include/asm/pgtable.h | 7 ++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
> index fc1189a..3ba4d93 100644
> --- a/arch/riscv/include/asm/io.h
> +++ b/arch/riscv/include/asm/io.h
> @@ -13,6 +13,7 @@
>
> #include <linux/types.h>
> #include <asm/mmiowb.h>
> +#include <asm/pgtable.h>
>
> extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
>
> @@ -162,6 +163,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
> #endif
>
> /*
> + * I/O port access constants.
> + */
> +#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
> +#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
> +
> +/*
> * Emulation routines for the port-mapped IO space used by some PCI drivers.
> * These are defined as being "fully synchronous", but also "not guaranteed to
> * be fully ordered with respect to other memory and I/O operations". We're
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 7fc5e4a..d78cc74 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -7,6 +7,7 @@
> #define _ASM_RISCV_PGTABLE_H
>
> #include <linux/mmzone.h>
> +#include <linux/sizes.h>
>
> #include <asm/pgtable-bits.h>
>
> @@ -88,6 +89,7 @@ extern pgd_t swapper_pg_dir[];
> #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
> #define VMALLOC_END (PAGE_OFFSET - 1)
> #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
> +#define PCI_IO_SIZE SZ_16M
>
> /*
> * Roughly size the vmemmap space to be large enough to fit enough
> @@ -102,7 +104,10 @@ extern pgd_t swapper_pg_dir[];
>
> #define vmemmap ((struct page *)VMEMMAP_START)
>
> -#define FIXADDR_TOP (VMEMMAP_START)
> +#define PCI_IO_END VMEMMAP_START
> +#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
> +#define FIXADDR_TOP PCI_IO_START
> +
> #ifdef CONFIG_64BIT
> #define FIXADDR_SIZE PMD_SIZE
> #else
>
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next prev parent reply other threads:[~2019-10-24 16:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-24 9:14 [PATCH] RISC-V: Add PCIe I/O BAR memory mapping Yash Shah
2019-10-24 16:24 ` Logan Gunthorpe [this message]
2019-10-24 16:51 ` Paul Walmsley
2019-10-24 17:07 ` Logan Gunthorpe
2019-10-25 6:35 ` Yash Shah
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