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From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Christophe JAILLET <christophe.jaillet@wanadoo.fr>,
	<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Walker Chen <walker.chen@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, Conor Dooley <conor@kernel.org>
Subject: Re: [PATCH v8 2/3] clocksource: Add JH7110 timer driver
Date: Thu, 21 Dec 2023 09:50:10 +0800	[thread overview]
Message-ID: <ec9f653d-7078-4efc-b1b6-bbd7a74a1c18@starfivetech.com> (raw)
In-Reply-To: <CAJM55Z_X9b=TJt7343kQ68ndN1MvH-rFM9hyEZMJRvQnOk72Yg@mail.gmail.com>

On 2023/12/20 21:59, Emil Renner Berthing wrote:
> Xingyu Wu wrote:
>> Add timer driver for the StarFive JH7110 SoC and select it by
>> CONFIG_SOC_STARFIVE.
>>
>> This timer has four free-running and independent 32-bit counters.
>> Each channel(counter) can trigger an interrupt when timeout even
>> CPU is sleeping. So this timer is used as global timer and register
>> clockevent for each CPU core after riscv-timer registration on the
>> StarFive JH7110 SoC.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>>  MAINTAINERS                        |   7 +
>>  arch/riscv/Kconfig.socs            |   1 +
>>  drivers/clocksource/Kconfig        |   9 +
>>  drivers/clocksource/Makefile       |   1 +
>>  drivers/clocksource/timer-jh7110.c | 360 +++++++++++++++++++++++++++++
>>  include/linux/cpuhotplug.h         |   1 +
>>  6 files changed, 379 insertions(+)
>>  create mode 100644 drivers/clocksource/timer-jh7110.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 9104430e148e..fe0e803606a5 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -20617,6 +20617,13 @@ S:	Maintained
>>  F:	Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml
>>  F:	sound/soc/starfive/jh7110_tdm.c
>>
>> +STARFIVE JH7110 TIMER DRIVER
>> +M:	Samin Guo <samin.guo@starfivetech.com>
> 
> Last time I sent a mail to samin.guo@starfivetech.com it bounced. Was that just
> a temporary error?
> 
> /Emil

Oh, This email has been deactivated and I don't have his other personal email.
I had dropped it in the driver but forget it here.
Will fix.

Thanks,
Xingyu Wu

> 
>> +M:	Xingyu Wu <xingyu.wu@starfivetech.com>
>> +S:	Supported
>> +F:	Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>> +F:	drivers/clocksource/timer-jh7110.c
>> +
>>  STARFIVE JH71X0 CLOCK DRIVERS
>>  M:	Emil Renner Berthing <kernel@esmil.dk>
>>  M:	Hal Feng <hal.feng@starfivetech.com>


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  reply	other threads:[~2023-12-21  1:59 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-19 14:53 [PATCH v8 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Xingyu Wu
2023-12-19 14:54 ` [PATCH v8 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC Xingyu Wu
2023-12-19 14:54 ` [PATCH v8 2/3] clocksource: Add JH7110 timer driver Xingyu Wu
2023-12-20 13:59   ` Emil Renner Berthing
2023-12-21  1:50     ` Xingyu Wu [this message]
2024-02-27 16:32   ` Thomas Gleixner
2023-12-19 14:54 ` [PATCH v8 3/3] riscv: dts: jh7110: starfive: Add timer node Xingyu Wu
2024-02-27  1:26 ` 回复: [PATCH v8 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Xingyu Wu

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