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Tue, 03 Sep 2019 11:48:53 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id r187sm11696625pfc.105.2019.09.03.11.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 11:48:52 -0700 (PDT) Date: Tue, 03 Sep 2019 11:48:52 -0700 (PDT) X-Google-Original-Date: Tue, 03 Sep 2019 11:48:19 PDT (-0700) Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode In-Reply-To: <20190828061146.GA21670@lst.de> From: Palmer Dabbelt To: Christoph Hellwig Message-ID: Mime-Version: 1.0 (MHng) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190903_114854_035079_F6AA5155 X-CRM114-Status: GOOD ( 11.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Damien Le Moal , linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Christoph Hellwig Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 27 Aug 2019 23:11:46 PDT (-0700), Christoph Hellwig wrote: > On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote: >> clint0 would be version 0 of the clint, with is the core-local interrupt >> controller in rocket chip. It should be "sifive,clint-1.0.0", not >> "riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of >> legacy device trees floating around, but I'm only considering what's been >> upstream to be actually part of the spec. >> >> In this case the code should match on a "sifive,clint-1.0.0", and the >> device trees should be fixed up to match. We match on "riscv,plic0" for >> legacy systems, and I guess it makes sense to do something similar here. > > IFF we decided to change it I'd rather separate DT noes for the ipi > bank vs timecmp register vs timeval to support variable layouts. The > downside is that we can't just boot on unmodified upstream qemu, which > has used the "riscv,clint0" for years. Like I alluded to above, matching on "riscv,clint0" seems reasonable to me as it's a defacto standard -- we'll just have to make sure that if we ever end up with a RISC-V CLINT that the DT entry is something else. As far as splitting the memory maps goes, I don't have a strong opinion but it seems like that'll introduce more complexity than it's worth. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv