From: Punit Agrawal <punit1.agrawal@toshiba.co.jp>
To: John Kacur <jkacur@redhat.com>
Cc: Punit Agrawal <punit1.agrawal@toshiba.co.jp>,
dwagner@suse.de, "Ahmed S . Darwish" <a.darwish@linutronix.de>,
linux-rt-users@vger.kernel.org, binh1.tranhai@toshiba.co.jp,
Daniel Sangorrin <daniel.sangorrin@toshiba.co.jp>
Subject: [rteval PATCH 1/2] rteval: cyclictest.py: Make 'model name' optional
Date: Tue, 26 Jan 2021 11:12:40 +0900 [thread overview]
Message-ID: <20210126021241.112944-2-punit1.agrawal@toshiba.co.jp> (raw)
In-Reply-To: <20210126021241.112944-1-punit1.agrawal@toshiba.co.jp>
Certain architectures such as arm64 don't have a "model name" in
/proc/cpuinfo. Relax the requirement to include the model name in the
description to allow running rteval on such machines.
Signed-off-by: Punit Agrawal <punit1.agrawal@toshiba.co.jp>
---
rteval/modules/measurement/cyclictest.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/rteval/modules/measurement/cyclictest.py b/rteval/modules/measurement/cyclictest.py
index 232bd6b..afe87f7 100644
--- a/rteval/modules/measurement/cyclictest.py
+++ b/rteval/modules/measurement/cyclictest.py
@@ -217,13 +217,13 @@ class Cyclictest(rtevalModulePrototype):
for core in self.__cpus:
self.__cyclicdata[core] = RunData(core, 'core', self.__priority,
logfnc=self._log)
- self.__cyclicdata[core].description = info[core]['model name']
+ self.__cyclicdata[core].description = info[core].get('model name', '')
# Create a RunData object for the overall system
self.__cyclicdata['system'] = RunData('system',
'system', self.__priority,
logfnc=self._log)
- self.__cyclicdata['system'].description = ("(%d cores) " % self.__numcores) + info['0']['model name']
+ self.__cyclicdata['system'].description = ("(%d cores) " % self.__numcores) + info['0'].get('model name', '')
if self.__sparse:
self._log(Log.DEBUG, "system using %d cpu cores" % self.__numcores)
--
2.29.2
next prev parent reply other threads:[~2021-01-26 4:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-26 2:12 [rteval PATCH 0/2] Relax some architecture specific constraints Punit Agrawal
2021-01-26 2:12 ` Punit Agrawal [this message]
2021-02-22 20:16 ` [rteval PATCH 1/2] rteval: cyclictest.py: Make 'model name' optional John Kacur
2021-02-24 1:49 ` Punit Agrawal
2021-01-26 2:12 ` [rteval PATCH 2/2] rteval: cyclictest.py: Make build targets architecture independent Punit Agrawal
2021-02-22 20:18 ` John Kacur
2021-02-22 0:31 ` [rteval PATCH 0/2] Relax some architecture specific constraints Punit Agrawal
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