From: Sylwester Nawrocki <s.nawrocki@samsung.com>
To: Marian Mihailescu <mihailescu2m@gmail.com>
Cc: linux-samsung-soc@vger.kernel.org, linux-clk <linux-clk@vger.kernel.org>
Subject: Re: [PATCH] clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
Date: Tue, 29 Oct 2019 11:36:50 +0100 [thread overview]
Message-ID: <97a6583c-3c5c-40c0-3bcf-9017e9bc2773@samsung.com> (raw)
In-Reply-To: <20191029005025.4476-1-mihailescu2m@gmail.com>
On 10/29/19 01:50, Marian Mihailescu wrote:
> Save and restore top PLL related configuration registers for big (APLL)
> and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
> were reset to default values after suspend/resume cycle and performance
> after system resume was affected when performance governor has been selected.
>
> Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")
> Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
Patch applied, thank you.
Please remember to also Cc in future any clk patches to the linux-clk@vger.kernel.org
mailing list.
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 403b5a367a5b..3a991ca1ee36 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
> GATE_BUS_CPU,
> GATE_SCLK_CPU,
> CLKOUT_CMU_CPU,
> + APLL_CON0,
> + KPLL_CON0,
> CPLL_CON0,
> DPLL_CON0,
> EPLL_CON0,
prev parent reply other threads:[~2019-10-29 10:36 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20191029005041epcas3p3be88dd1df53b124f5642259784d8b1c6@epcas3p3.samsung.com>
2019-10-29 0:50 ` [PATCH] clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume Marian Mihailescu
2019-10-29 10:36 ` Sylwester Nawrocki [this message]
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