From: Peter Griffin <peter.griffin@linaro.org>
To: alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
James.Bottomley@HansenPartnership.com,
martin.petersen@oracle.com
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
tudor.ambarus@linaro.org, andre.draszik@linaro.org,
saravanak@google.com, willmcvicker@google.com,
kernel-team@android.com, Peter Griffin <peter.griffin@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v3 2/6] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
Date: Fri, 26 Apr 2024 13:20:00 +0100 [thread overview]
Message-ID: <20240426122004.2249178-3-peter.griffin@linaro.org> (raw)
In-Reply-To: <20240426122004.2249178-1-peter.griffin@linaro.org>
This option is intended to be set on platforms whose ufspr
registers are only accessible via smc call (such as gs101).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
---
drivers/ufs/host/ufs-exynos.c | 4 +++-
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index e8d3302f6df0..66e52c3607e2 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -1186,7 +1186,9 @@ static int exynos_ufs_init(struct ufs_hba *hba)
if (ret)
goto out;
exynos_ufs_specify_phy_time_attr(ufs);
- exynos_ufs_config_smu(ufs);
+
+ if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
+ exynos_ufs_config_smu(ufs);
hba->host->dma_alignment = SZ_4K - 1;
return 0;
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index a4bd6646d7f1..0fc21b6bbfcd 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -221,6 +221,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
+#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
};
#define for_each_ufs_rx_lane(ufs, i) \
--
2.44.0.769.g3c40516874-goog
next prev parent reply other threads:[~2024-04-26 12:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-26 12:19 [PATCH v3 0/6] ufs-exynos support for Tensor GS101 Peter Griffin
2024-04-26 12:19 ` [PATCH v3 1/6] dt-bindings: ufs: exynos-ufs: Add gs101 compatible Peter Griffin
2024-04-26 19:11 ` Rob Herring
2024-04-26 12:20 ` Peter Griffin [this message]
2024-04-26 12:20 ` [PATCH v3 3/6] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option Peter Griffin
2024-04-26 12:20 ` [PATCH v3 4/6] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz Peter Griffin
2024-04-26 12:20 ` [PATCH v3 5/6] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata Peter Griffin
2024-04-26 12:20 ` [PATCH v3 6/6] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC Peter Griffin
2024-05-07 1:38 ` [PATCH v3 0/6] ufs-exynos support for Tensor GS101 Martin K. Petersen
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