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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	dmaengine <dmaengine@vger.kernel.org>,
	Linux MMC List <linux-mmc@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
	Prabhakar <prabhakar.csengg@gmail.com>
Subject: Re: [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree
Date: Mon, 4 May 2020 12:28:39 +0200	[thread overview]
Message-ID: <CAMuHMdW=njc2Vvu+7WHgikWOMtWCWTMmxeYLWLP0Z1TyStiaFg@mail.gmail.com> (raw)
In-Reply-To: <1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Sun, May 3, 2020 at 11:47 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC,
> CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer
> and the required clock descriptions.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7742.dtsi

> +               icram2: sram@e6300000 {
> +                       compatible = "mmio-sram";
> +                       reg = <0 0xe6300000 0 0x40000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0 0 0xe6300000 0x40000>;
> +               };
> +
> +               scifa2: serial@e6c60000 {
> +                       compatible = "renesas,scifa-r8a7742",
> +                                    "renesas,rcar-gen2-scifa", "renesas,scifa";
> +                       reg = <0 0xe6c60000 0 0x40>;
> +                       interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 202>;
> +                       clock-names = "fck";
> +                       dmas = <&dmac0 0x27>, <&dmac0 0x28>,
> +                              <&dmac1 0x27>, <&dmac1 0x28>;
> +                       dma-names = "tx", "rx", "tx", "rx";
> +                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> +                       resets = <&cpg 202>;
> +                       status = "disabled";
> +               };
> +
> +               mmcif1: mmc@ee220000 {
> +                       compatible = "renesas,mmcif-r8a7742",
> +                                    "renesas,sh-mmcif";
> +                       reg = <0 0xee220000 0 0x80>;
> +                       interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 305>;
> +                       dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
> +                              <&dmac1 0xe1>, <&dmac1 0xe2>;
> +                       dma-names = "tx", "rx", "tx", "rx";
> +                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> +                       resets = <&cpg 305>;
> +                       reg-io-width = <4>;
> +                       status = "disabled";
> +                       max-frequency = <97500000>;
> +               };
> +
> +               dmac0: dma-controller@e6700000 {
> +                       compatible = "renesas,dmac-r8a7742",
> +                                    "renesas,rcar-dmac";
> +                       reg = <0 0xe6700000 0 0x20000>;
> +                       interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "error",
> +                                         "ch0", "ch1", "ch2", "ch3",
> +                                         "ch4", "ch5", "ch6", "ch7",
> +                                         "ch8", "ch9", "ch10", "ch11",
> +                                         "ch12", "ch13", "ch14";
> +                       clocks = <&cpg CPG_MOD 219>;
> +                       clock-names = "fck";
> +                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> +                       resets = <&cpg 219>;
> +                       #dma-cells = <1>;
> +                       dma-channels = <15>;
> +               };
> +
> +               dmac1: dma-controller@e6720000 {
> +                       compatible = "renesas,dmac-r8a7742",
> +                                    "renesas,rcar-dmac";
> +                       reg = <0 0xe6720000 0 0x20000>;
> +                       interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "error",
> +                                         "ch0", "ch1", "ch2", "ch3",
> +                                         "ch4", "ch5", "ch6", "ch7",
> +                                         "ch8", "ch9", "ch10", "ch11",
> +                                         "ch12", "ch13", "ch14";
> +                       clocks = <&cpg CPG_MOD 218>;
> +                       clock-names = "fck";
> +                       power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
> +                       resets = <&cpg 218>;
> +                       #dma-cells = <1>;
> +                       dma-channels = <15>;
> +               };

To preserve sort order, the DMAC nodes should be moved up.
No need to resend, will fix up while applying.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.8.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2020-05-04 10:28 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-03 21:46 [PATCH v2 00/10] Add initial support for R8A7742/RZG1H SoC and iW-RainboW-G21D-Qseven development board support Lad Prabhakar
2020-05-03 21:46 ` [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Lad Prabhakar
2020-05-12 22:17   ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 02/10] pinctrl: sh-pfc: r8a7790: Add " Lad Prabhakar
2020-05-04 10:20   ` Geert Uytterhoeven
2020-05-04 13:41     ` Lad, Prabhakar
2020-05-03 21:46 ` [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings Lad Prabhakar
2020-05-12 22:20   ` Rob Herring
2020-05-28 19:36     ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 04/10] dt-bindings: mmc: renesas,mmcif: Document r8a7742 DT bindings Lad Prabhakar
2020-05-04 10:26   ` Geert Uytterhoeven
2020-05-04 13:43     ` Lad, Prabhakar
2020-05-03 21:46 ` [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support Lad Prabhakar
2020-05-12 22:21   ` Rob Herring
2020-08-27 11:08   ` Lad, Prabhakar
2020-09-03  7:12     ` Vinod Koul
2020-05-03 21:46 ` [PATCH v2 06/10] ARM: dts: r8a7742: Initial SoC device tree Lad Prabhakar
2020-05-04 10:28   ` Geert Uytterhoeven [this message]
2020-05-03 21:46 ` [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module Lad Prabhakar
2020-05-04 11:21   ` Geert Uytterhoeven
2020-05-12 22:21   ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board Lad Prabhakar
2020-05-04 11:21   ` Geert Uytterhoeven
2020-05-12 22:21   ` Rob Herring
2020-05-03 21:46 ` [PATCH v2 09/10] ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM Lad Prabhakar
2020-05-04 13:01   ` Geert Uytterhoeven
2020-05-04 14:20     ` Lad, Prabhakar
2020-05-04 14:29       ` Geert Uytterhoeven
2020-05-03 21:46 ` [PATCH v2 10/10] ARM: dts: r8a7742-iwg21d-q7: Add support for iWave G21D-Q7 board based on RZ/G1H Lad Prabhakar
2020-05-04 13:09   ` Geert Uytterhoeven
2020-06-05 12:51   ` Geert Uytterhoeven
2020-06-05 19:04     ` Lad, Prabhakar

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