From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: x86@kernel.org, linux-sgx@vger.kernel.org
Cc: akpm@linux-foundation.org, dave.hansen@intel.com,
sean.j.christopherson@intel.com, nhorman@redhat.com,
npmccallum@redhat.com, serge.ayoun@intel.com,
shay.katz-zamir@intel.com, haitao.huang@intel.com,
andriy.shevchenko@linux.intel.com, tglx@linutronix.de,
kai.svahn@intel.com, bp@alien8.de, josh@joshtriplett.org,
luto@kernel.org,
Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Subject: [PATCH v18 02/25] x86/cpufeatures: Add SGX sub-features (as Linux-defined bits)
Date: Sat, 22 Dec 2018 01:11:31 +0200 [thread overview]
Message-ID: <20181221231154.6120-3-jarkko.sakkinen@linux.intel.com> (raw)
In-Reply-To: <20181221231154.6120-1-jarkko.sakkinen@linux.intel.com>
From: Sean Christopherson <sean.j.christopherson@intel.com>
CPUID_12_EAX is an Intel-defined feature bits leaf dedicated for SGX
that enumerates the SGX instruction sets that are supported by the
CPU, e.g. SGX1, SGX2, etc... Because Linux currently only cares about
two bits (SGX1 and SGX2) and there are currently only four documented
bits in total, relocate the bits to Linux-defined word 8 to conserve
space.
But, keep the bit positions identical between the Intel-defined value
and the Linux-defined value, e.g. keep SGX1 at bit 0. This allows KVM
to use its existing code for probing guest CPUID bits using Linux's
X86_FEATURE_* definitions. To do so, shift around some existing bits
to effectively reserve bits 0-7 of word 8 for SGX sub-features.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
---
arch/x86/include/asm/cpufeatures.h | 22 ++++++++++++++++------
arch/x86/include/asm/disabled-features.h | 6 +++++-
arch/x86/kernel/cpu/scattered.c | 2 ++
tools/arch/x86/include/asm/cpufeatures.h | 21 +++++++++++++++------
4 files changed, 38 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index da7fed4939a3..94d2b1cf8ee0 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -222,12 +222,22 @@
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
-/* Virtualization flags: Linux defined, word 8 */
-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
-#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
+/*
+ * Scattered Intel features: Linux defined, word 8.
+ *
+ * Note that the bit location of the SGX features is meaningful as KVM expects
+ * the Linux defined bit to match the Intel defined bit, e.g. X86_FEATURE_SGX1
+ * must remain at bit 0, SGX2 at bit 1, etc...
+ */
+#define X86_FEATURE_SGX1 ( 8*32+ 0) /* SGX1 leaf functions */
+#define X86_FEATURE_SGX2 ( 8*32+ 1) /* SGX2 leaf functions */
+/* Bits [0:7] are reserved for SGX */
+
+#define X86_FEATURE_TPR_SHADOW ( 8*32+ 8) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI ( 8*32+ 9) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY ( 8*32+10) /* Intel FlexPriority */
+#define X86_FEATURE_EPT ( 8*32+11) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID ( 8*32+12) /* Intel Virtual Processor ID */
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index 1e6da9b8c6f6..140d0c64456b 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -28,12 +28,16 @@
# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31))
# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31))
# define DISABLE_PCID 0
+# define DISABLE_SGX1 0
+# define DISABLE_SGX2 0
#else
# define DISABLE_VME 0
# define DISABLE_K6_MTRR 0
# define DISABLE_CYRIX_ARR 0
# define DISABLE_CENTAUR_MCR 0
# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31))
+# define DISABLE_SGX1 (1<<(X86_FEATURE_SGX1 & 31))
+# define DISABLE_SGX2 (1<<(X86_FEATURE_SGX2 & 31))
#endif /* CONFIG_X86_64 */
#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
@@ -73,7 +77,7 @@
#define DISABLED_MASK5 0
#define DISABLED_MASK6 0
#define DISABLED_MASK7 (DISABLE_PTI)
-#define DISABLED_MASK8 0
+#define DISABLED_MASK8 (DISABLE_SGX1|DISABLE_SGX2)
#define DISABLED_MASK9 (DISABLE_MPX|DISABLE_SGX_CORE)
#define DISABLED_MASK10 0
#define DISABLED_MASK11 0
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 772c219b6889..f7f0970b8f89 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -26,6 +26,8 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
+ { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
+ { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 89a048c2faec..9cc7628b9845 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -222,12 +222,21 @@
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
-/* Virtualization flags: Linux defined, word 8 */
-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
-#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
+/*
+ * Scattered Intel features: Linux defined, word 8.
+ *
+ * Note that the bit numbers of the SGX features are meaningful as KVM expects
+ * the Linux defined bit to match the Intel defined bit, e.g. X86_FEATURE_SGX1
+ * must remain at bit 0, SGX2 at bit 1, etc...
+ */
+#define X86_FEATURE_SGX1 ( 8*32+ 0) /* SGX1 leaf functions */
+#define X86_FEATURE_SGX2 ( 8*32+ 1) /* SGX2 leaf functions */
+
+#define X86_FEATURE_TPR_SHADOW ( 8*32+ 8) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI ( 8*32+ 9) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY ( 8*32+10) /* Intel FlexPriority */
+#define X86_FEATURE_EPT ( 8*32+11) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID ( 8*32+12) /* Intel Virtual Processor ID */
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
--
2.19.1
next prev parent reply other threads:[~2018-12-21 23:12 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-21 23:11 [PATCH v18 00/25] Intel SGX1 support Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 01/25] x86/cpufeatures: Add Intel-defined SGX feature bit Jarkko Sakkinen
2018-12-21 23:11 ` Jarkko Sakkinen [this message]
2018-12-21 23:11 ` [PATCH v18 03/25] x86/msr: Add IA32_FEATURE_CONTROL.SGX_ENABLE definition Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 04/25] x86/cpufeatures: Add Intel-defined SGX_LC feature bit Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 05/25] x86/msr: Add SGX Launch Control MSR definitions Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 06/25] x86/mm: x86/sgx: Add new 'PF_SGX' page fault error code bit Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 07/25] x86/mm: x86/sgx: Signal SIGSEGV for userspace #PFs w/ PF_SGX Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 08/25] x86/cpu/intel: Detect SGX support and update caps appropriately Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 09/25] x86/sgx: Define SGX1 and SGX2 ENCLS leafs Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 10/25] x86/sgx: Add ENCLS architectural error codes Jarkko Sakkinen
2018-12-24 5:17 ` Jethro Beekman
2018-12-24 11:53 ` Jarkko Sakkinen
2019-01-02 20:54 ` Sean Christopherson
2018-12-21 23:11 ` [PATCH v18 11/25] x86/sgx: Add SGX1 and SGX2 architectural data structures Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 12/25] x86/sgx: Add definitions for SGX's CPUID leaf and variable sub-leafs Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 13/25] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 14/25] x86/sgx: Enumerate and track EPC sections Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 15/25] x86/sgx: Add functions to allocate and free EPC pages Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 16/25] x86/sgx: Add sgx_einit() for initializing enclaves Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 17/25] x86/mpx: pass @mm to kernel_managing_mpx_tables() in mpx_notify_unmap() Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 18/25] x86/sgx: Add the Linux SGX Enclave Driver Jarkko Sakkinen
2018-12-24 5:36 ` Jethro Beekman
2018-12-24 11:55 ` Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 19/25] x86/sgx: Add provisioning Jarkko Sakkinen
2018-12-24 5:36 ` Jethro Beekman
2018-12-24 11:57 ` Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 20/25] x86/sgx: Add swapping code to the SGX driver Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 21/25] x86/sgx: Add a simple swapper for the EPC memory manager Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 22/25] x86/sgx: ptrace() support for the SGX driver Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 23/25] x86/sgx: SGX documentation Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 24/25] selftests/x86: Add a selftest for SGX Jarkko Sakkinen
2018-12-21 23:11 ` [PATCH v18 25/25] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181221231154.6120-3-jarkko.sakkinen@linux.intel.com \
--to=jarkko.sakkinen@linux.intel.com \
--cc=akpm@linux-foundation.org \
--cc=andriy.shevchenko@linux.intel.com \
--cc=bp@alien8.de \
--cc=dave.hansen@intel.com \
--cc=haitao.huang@intel.com \
--cc=josh@joshtriplett.org \
--cc=kai.svahn@intel.com \
--cc=linux-sgx@vger.kernel.org \
--cc=luto@kernel.org \
--cc=nhorman@redhat.com \
--cc=npmccallum@redhat.com \
--cc=sean.j.christopherson@intel.com \
--cc=serge.ayoun@intel.com \
--cc=shay.katz-zamir@intel.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).