From: Borislav Petkov <bp@alien8.de>
To: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org,
linux-sgx@vger.kernel.org, akpm@linux-foundation.org,
dave.hansen@intel.com, sean.j.christopherson@intel.com,
nhorman@redhat.com, npmccallum@redhat.com, serge.ayoun@intel.com,
shay.katz-zamir@intel.com, haitao.huang@intel.com,
andriy.shevchenko@linux.intel.com, tglx@linutronix.de,
kai.svahn@intel.com, josh@joshtriplett.org, luto@kernel.org,
kai.huang@intel.com, rientjes@google.com, cedric.xing@intel.com
Subject: Re: [PATCH v22 06/24] x86/sgx: Add SGX microarchitectural data structures
Date: Fri, 27 Sep 2019 18:27:35 +0200 [thread overview]
Message-ID: <20190927162735.GC23002@zn.tnic> (raw)
In-Reply-To: <20190903142655.21943-7-jarkko.sakkinen@linux.intel.com>
On Tue, Sep 03, 2019 at 05:26:37PM +0300, Jarkko Sakkinen wrote:
> Define the SGX microarchitectural data structures used by various SGX
> opcodes. This is not an exhaustive representation of all SGX data
> structures but only those needed by the kernel.
>
> [1] Intel SDM: 37.6 INTEL® SGX DATA STRUCTURES OVERVIEW
That footnote is not being referred to. Just make it a sentence.
Btw, you could tell your SDM folks to fix formulations like:
"The use of EAX is implied implicitly by the ENCLS, ENCLU, and ENCLV
^^^^^^^^^^^^^^^^^^^
instructions.... The use of additional registers does not use ModR/M
encoding and is implied implicitly by the respective leaf function
^^^^^^^^^^^^^^^^^^^
index."
"implied" alone wasn't enough I guess. :)
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
> Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> ---
> arch/x86/kernel/cpu/sgx/arch.h | 423 +++++++++++++++++++++++++++++++++
> 1 file changed, 423 insertions(+)
> create mode 100644 arch/x86/kernel/cpu/sgx/arch.h
>
> diff --git a/arch/x86/kernel/cpu/sgx/arch.h b/arch/x86/kernel/cpu/sgx/arch.h
> new file mode 100644
> index 000000000000..725a47f9f761
> --- /dev/null
> +++ b/arch/x86/kernel/cpu/sgx/arch.h
> @@ -0,0 +1,423 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
> +/**
> + * Copyright(c) 2016-18 Intel Corporation.
> + *
> + * Contains data structures defined by the SGX architecture. Data structures
> + * defined by the Linux software stack should not be placed here.
> + */
> +#ifndef _ASM_X86_SGX_ARCH_H
> +#define _ASM_X86_SGX_ARCH_H
> +
> +#include <linux/types.h>
> +
> +#define SGX_CPUID 0x12
> +#define SGX_CPUID_FIRST_VARIABLE_SUB_LEAF 2
> +
> +/**
> + * enum sgx_sub_leaf_types - SGX CPUID variable sub-leaf types
> + * %SGX_CPUID_SUB_LEAF_INVALID: Indicates this sub-leaf is invalid.
> + * %SGX_CPUID_SUB_LEAF_EPC_SECTION: Sub-leaf enumerates an EPC section.
> + */
> +enum sgx_sub_leaf_types {
> + SGX_CPUID_SUB_LEAF_INVALID = 0x0,
> + SGX_CPUID_SUB_LEAF_EPC_SECTION = 0x1,
> +};
> +
> +#define SGX_CPUID_SUB_LEAF_TYPE_MASK GENMASK(3, 0)
> +
> +/**
> + * enum sgx_encls_leaves - ENCLS leaf functions
> + * %SGX_ECREATE: Create an enclave.
> + * %SGX_EADD: Add a page to an uninitialized enclave.
> + * %SGX_EINIT: Initialize an enclave, i.e. launch an enclave.
> + * %SGX_EREMOVE: Remove a page from an enclave.
> + * %SGX_EDBGRD: Read a word from an enclve (peek).
> + * %SGX_EDBGWR: Write a word to an enclave (poke).
> + * %SGX_EEXTEND: Measure 256 bytes of an added enclave page.
> + * %SGX_ELDB: Load a swapped page in blocked state.
> + * %SGX_ELDU: Load a swapped page in unblocked state.
> + * %SGX_EBLOCK: Change page state to blocked i.e. entering hardware
> + * threads cannot access it and create new TLB entries.
> + * %SGX_EPA: Create a Version Array (VA) page used to store isvsvn
> + * number for a swapped EPC page.
> + * %SGX_EWB: Swap an enclave page to the regular memory. Checks that
> + * all threads have exited that were in the previous
> + * shoot-down sequence.
> + * %SGX_ETRACK: Start a new shoot down sequence. Used to together with
> + * EBLOCK to make sure that a page is safe to swap.
> + * %SGX_EAUG: Add a page to an initialized enclave.
> + * %SGX_EMODPR: Restrict an EPC page's permissions.
> + * %SGX_EMODT: Modify the page type of an EPC page.
> + */
> +enum sgx_encls_leaves {
> + SGX_ECREATE = 0x00,
> + SGX_EADD = 0x01,
> + SGX_EINIT = 0x02,
> + SGX_EREMOVE = 0x03,
> + SGX_EDGBRD = 0x04,
> + SGX_EDGBWR = 0x05,
> + SGX_EEXTEND = 0x06,
> + SGX_ELDB = 0x07,
> + SGX_ELDU = 0x08,
> + SGX_EBLOCK = 0x09,
> + SGX_EPA = 0x0A,
> + SGX_EWB = 0x0B,
> + SGX_ETRACK = 0x0C,
> + SGX_EAUG = 0x0D,
> + SGX_EMODPR = 0x0E,
> + SGX_EMODT = 0x0F,
> +};
> +
> +#define SGX_MODULUS_SIZE 384
> +
> +/**
> + * enum sgx_miscselect - additional information to an SSA frame
> + * %SGX_MISC_EXINFO: Report #PF or #GP to the SSA frame.
> + *
> + * Save State Area (SSA) is a stack inside the enclave used to store processor
> + * state when an exception or interrupt occurs. This enum defines additional
> + * information stored to an SSA frame.
> + */
> +enum sgx_miscselect {
> + SGX_MISC_EXINFO = BIT(0),
> +};
> +
> +#define SGX_MISC_RESERVED_MASK GENMASK_ULL(63, 1)
> +
> +#define SGX_SSA_GPRS_SIZE 182
> +#define SGX_SSA_MISC_EXINFO_SIZE 16
> +
> +/**
> + * enum sgx_attributes - the attributes field in &struct sgx_secs
> + * %SGX_ATTR_INIT: Enclave can be entered (is initialized).
> + * %SGX_ATTR_DEBUG: Allow ENCLS(EDBGRD) and ENCLS(EDBGWR).
> + * %SGX_ATTR_MODE64BIT: Tell that this a 64-bit enclave.
> + * %SGX_ATTR_PROVISIONKEY: Allow to use provisioning keys for remote
> + * attestation.
> + * %SGX_ATTR_KSS: Allow to use key separation and sharing (KSS).
> + * %SGX_ATTR_EINITTOKENKEY: Allow to use token signing key that is used to
> + * sign cryptographic tokens that can be passed to
> + * EINIT as an authorization to run an enclave.
> + */
> +enum sgx_attribute {
> + SGX_ATTR_INIT = BIT(0),
> + SGX_ATTR_DEBUG = BIT(1),
> + SGX_ATTR_MODE64BIT = BIT(2),
> + SGX_ATTR_PROVISIONKEY = BIT(4),
> + SGX_ATTR_EINITTOKENKEY = BIT(5),
> + SGX_ATTR_KSS = BIT(7),
> +};
> +
> +#define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) | BIT_ULL(7) | GENMASK_ULL(63, 8))
Looking how bit 7 is part of the reserved mask but you have it above
as SGX_ATTR_KSS too. Bit 6, OTOH, is not mentioned anywhere and it
very much looks like you need to have BIT_ULL(6) above as part of the
reserved mask instead of bit 7.
Hmmm?
> +#define SGX_ATTR_ALLOWED_MASK (SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | \
> + SGX_ATTR_KSS)
> +#define SGX_SECS_RESERVED1_SIZE 24
> +#define SGX_SECS_RESERVED2_SIZE 32
> +#define SGX_SECS_RESERVED3_SIZE 96
> +#define SGX_SECS_RESERVED4_SIZE 3836
I'd make those defines shorter...
> +
> +/**
> + * struct sgx_secs - SGX Enclave Control Structure (SECS)
> + * @size: size of the address space
> + * @base: base address of the address space
> + * @ssa_frame_size: size of an SSA frame
> + * @miscselect: additional information stored to an SSA frame
> + * @attributes: attributes for enclave
> + * @xfrm: XSave-Feature Request Mask (subset of XCR0)
> + * @mrenclave: SHA256-hash of the enclave contents
> + * @mrsigner: SHA256-hash of the public key used to sign the SIGSTRUCT
> + * @isvprodid: a user-defined value that is used in key derivation
> + * @isvsvn: a user-defined value that is used in key derivation
> + *
> + * SGX Enclave Control Structure (SECS) is a special enclave page that is not
> + * visible in the address space. In fact, this structure defines the address
> + * range and other global attributes for the enclave and it is the first EPC
> + * page created for any enclave. It is moved from a temporary buffer to an EPC
> + * by the means of ENCLS(ECREATE) leaf.
> + */
> +struct sgx_secs {
> + u64 size;
> + u64 base;
> + u32 ssa_frame_size;
> + u32 miscselect;
> + u8 reserved1[SGX_SECS_RESERVED1_SIZE];
> + u64 attributes;
> + u64 xfrm;
> + u32 mrenclave[8];
> + u8 reserved2[SGX_SECS_RESERVED2_SIZE];
> + u32 mrsigner[8];
> + u8 reserved3[SGX_SECS_RESERVED3_SIZE];
> + u16 isvprodid;
> + u16 isvsvn;
> + u8 reserved4[SGX_SECS_RESERVED4_SIZE];
... so that they don't stick too much here.
...
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2019-09-27 16:27 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 14:26 [PATCH v22 00/24] Intel SGX foundations Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 01/24] x86/cpufeatures: x86/msr: Add Intel SGX hardware bits Jarkko Sakkinen
2019-09-24 15:28 ` Borislav Petkov
2019-09-24 16:11 ` Sean Christopherson
2019-09-24 16:25 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 02/24] x86/cpufeatures: x86/msr: Intel SGX Launch Control " Jarkko Sakkinen
2019-09-24 15:52 ` Borislav Petkov
2019-09-24 20:22 ` Sean Christopherson
2019-09-25 8:51 ` Borislav Petkov
2019-09-25 17:18 ` Sean Christopherson
2019-09-25 18:31 ` Borislav Petkov
2019-09-25 19:08 ` Sean Christopherson
2019-09-27 16:11 ` Jarkko Sakkinen
2019-09-25 14:09 ` Jarkko Sakkinen
2019-09-25 14:10 ` Jarkko Sakkinen
2019-09-25 14:38 ` Jarkko Sakkinen
2019-09-25 15:19 ` Borislav Petkov
2019-09-25 16:49 ` Sean Christopherson
2019-09-25 17:28 ` Borislav Petkov
2019-09-25 18:18 ` Sean Christopherson
2019-09-03 14:26 ` [PATCH v22 03/24] x86/mm: x86/sgx: Signal SIGSEGV with PF_SGX Jarkko Sakkinen
2019-09-24 16:04 ` Borislav Petkov
2019-09-25 14:16 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 04/24] x86/cpu/intel: Detect SGX supprt Jarkko Sakkinen
2019-09-24 16:13 ` Borislav Petkov
2019-09-24 17:43 ` Sean Christopherson
2019-09-24 18:21 ` Borislav Petkov
2019-09-25 14:46 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 05/24] x86/sgx: Add ENCLS architectural error codes Jarkko Sakkinen
2019-09-27 10:20 ` Borislav Petkov
2019-09-27 16:08 ` Jarkko Sakkinen
2019-09-27 17:20 ` Sean Christopherson
2019-10-01 20:23 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 06/24] x86/sgx: Add SGX microarchitectural data structures Jarkko Sakkinen
2019-09-27 16:27 ` Borislav Petkov [this message]
2019-10-01 19:10 ` Jarkko Sakkinen
2019-10-01 20:39 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 07/24] x86/sgx: Add wrappers for ENCLS leaf functions Jarkko Sakkinen
2019-10-04 9:45 ` Borislav Petkov
2019-10-04 18:56 ` Jarkko Sakkinen
2019-10-08 4:04 ` Sean Christopherson
2019-10-08 7:18 ` Borislav Petkov
2019-10-08 13:35 ` Sean Christopherson
2019-10-08 14:56 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 08/24] x86/sgx: Enumerate and track EPC sections Jarkko Sakkinen
2019-10-05 9:26 ` Borislav Petkov
2019-10-07 11:58 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 09/24] x86/sgx: Add functions to allocate and free EPC pages Jarkko Sakkinen
2019-10-05 16:44 ` Borislav Petkov
2019-10-07 14:50 ` Sean Christopherson
2019-10-08 9:09 ` Borislav Petkov
2019-10-08 13:31 ` Sean Christopherson
2019-10-07 17:55 ` Jarkko Sakkinen
2019-10-07 18:09 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 10/24] x86/sgx: Add sgx_einit() for wrapping ENCLS[EINIT] Jarkko Sakkinen
2019-10-08 17:30 ` Borislav Petkov
2019-10-08 17:45 ` Sean Christopherson
2019-10-08 17:46 ` Sean Christopherson
2019-10-08 17:53 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 11/24] mm: Introduce vm_ops->may_mprotect() Jarkko Sakkinen
2019-10-08 17:41 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 12/24] x86/sgx: Linux Enclave Driver Jarkko Sakkinen
2019-10-08 17:59 ` Borislav Petkov
2019-10-08 18:17 ` Sean Christopherson
2019-10-08 19:19 ` Borislav Petkov
2019-09-03 14:26 ` [PATCH v22 13/24] x86/sgx: Add provisioning Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 14/24] x86/sgx: Add a page reclaimer Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 15/24] x86/sgx: ptrace() support for the SGX driver Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 16/24] x86/vdso: Add support for exception fixup in vDSO functions Jarkko Sakkinen
2019-10-02 23:18 ` Jarkko Sakkinen
2019-10-02 23:45 ` Jarkko Sakkinen
2019-10-04 0:03 ` Sean Christopherson
2019-10-04 18:49 ` Jarkko Sakkinen
2019-10-04 0:15 ` Sean Christopherson
2019-10-04 18:52 ` Jarkko Sakkinen
2019-10-05 15:54 ` Sean Christopherson
2019-10-07 7:57 ` Jarkko Sakkinen
2019-10-07 8:10 ` Jarkko Sakkinen
2019-10-07 12:04 ` Jarkko Sakkinen
2019-10-08 4:54 ` Sean Christopherson
2019-10-05 18:39 ` Sean Christopherson
2019-10-07 8:01 ` Jarkko Sakkinen
2019-10-06 23:38 ` Jarkko Sakkinen
2019-10-06 23:40 ` Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 17/24] x86/fault: Add helper function to sanitize error code Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 18/24] x86/traps: Attempt to fixup exceptions in vDSO before signaling Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 19/24] x86/vdso: Add __vdso_sgx_enter_enclave() to wrap SGX enclave transitions Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 20/24] selftests/x86: Add a selftest for SGX Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 21/24] selftests/x86: Recurse into subdirectories Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 22/24] x86/sgx: Update MAINTAINERS Jarkko Sakkinen
2019-09-03 14:26 ` [PATCH v22 23/24] docs: x86/sgx: Document microarchitecture Jarkko Sakkinen
2019-09-27 18:15 ` Randy Dunlap
2019-09-03 14:26 ` [PATCH v22 24/24] docs: x86/sgx: Document kernel internals Jarkko Sakkinen
2019-09-27 17:07 ` Randy Dunlap
2019-10-01 19:34 ` Jarkko Sakkinen
2019-09-13 20:38 ` [PATCH v22 00/24] Intel SGX foundations Dave Hansen
2019-09-14 13:41 ` Jarkko Sakkinen
2019-09-14 15:32 ` Dave Hansen
2019-09-16 5:23 ` Jarkko Sakkinen
2019-09-24 17:20 ` Andy Lutomirski
2019-09-25 14:32 ` Jarkko Sakkinen
2019-10-02 23:42 ` Jarkko Sakkinen
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