From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Arnd Bergmann <arnd@arndb.de>,
Paul Burton <paulburton@kernel.org>,
Viresh Kumar <vireshk@kernel.org>,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Ralf Baechle <ralf@linux-mips.org>,
"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
arcml <linux-snps-arc@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/6] dmaengine: dw: Set DMA device max segment size parameter
Date: Fri, 8 May 2020 18:49:18 +0000 [thread overview]
Message-ID: <5c83eabd-08c9-fdae-d13f-49c177b6c5bf@synopsys.com> (raw)
In-Reply-To: <20200508112152.GI185537@smile.fi.intel.com>
On 5/8/20 4:21 AM, Andy Shevchenko wrote:
> Yeah, I have locally something like this and I didn't dare to upstream because
> there is an issue. We have this information per DMA controller, while we
> actually need this on per DMA channel basis.
>
> Above will work only for synthesized DMA with all channels having same block
> size. That's why above conditional is not needed anyway.
>
> OTOH, I never saw the DesignWare DMA to be synthesized differently (I remember
> that Intel Medfield has interesting settings, but I don't remember if DMA
> channels are different inside the same controller).
>
> Vineet, do you have any information that Synopsys customers synthesized DMA
> controllers with different channel characteristics inside one DMA IP?
The IP drivers are done by different teams, but I can try and ask around.
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parent reply other threads:[~2020-05-08 18:49 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20200508112152.GI185537@smile.fi.intel.com>]
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