Re: [PATCH v2] spi: spi-imx: fix mixing of native and gpio chipselects for imx51/imx53/imx6 variants

[Mark Brown <broonie@kernel.org>]

On Fri, 02 Jun 2023 13:57:30 +0200, Rasmus Villemoes wrote:
> Commit 87c614175bbf (spi: spi-imx: fix MX51_ECSPI_* macros when cs >
> 3) ensured that the argument passed to the macros was masked with &3,
> so that we no longer write outside the intended fields in the various
> control registers. When all chip selects are gpios, this works just
> fine.
> 
> However, when a mix of native and gpio chip selects are in use, that
> masking is too naive. Say, for example, that SS0 is muxed as native
> chip select, and there is also a chip at 4 (obviously with a gpio
> cs). In that case, when accessing the latter chip, both the SS0 pin
> and the gpio pin will be asserted low.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: spi-imx: fix mixing of native and gpio chipselects for imx51/imx53/imx6 variants
      commit: a34e0353a681bbdd0402825e25410c3236109f31

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

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Thanks,
Mark