On Sun, Sep 20, 2020 at 02:28:55PM +0300, Serge Semin wrote:

> -	/*
> -	 * SPI mode (SCPOL|SCPH)
> -	 * CTRLR0[ 8] Serial Clock Phase
> -	 * CTRLR0[ 9] Serial Clock Polarity
> -	 */
> -	cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
> -	cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;

> +		cr0 |= SSI_MOTO_SPI << DWC_SSI_CTRLR0_FRF_OFFSET;
> +		cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
> +		cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;

The new code seems less well commented than the old code here.