From: Conor Dooley <conor@kernel.org>
To: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
valentina.fernandezalanis@microchip.com
Subject: Re: [PATCH v2 1/3] spi: dt-bindings: Add num-cs property for mpfs-spi
Date: Tue, 14 May 2024 18:52:42 +0100 [thread overview]
Message-ID: <20240514-parmesan-enslave-444763e785ff@spud> (raw)
In-Reply-To: <20240514104508.938448-2-prajna.rajendrakumar@microchip.com>
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On Tue, May 14, 2024 at 11:45:06AM +0100, Prajna Rajendra Kumar wrote:
> The PolarFire SoC SPI "hard" controller supports eight CS lines, out of
> which only one CS line is physically wired. The default value of
> 'num-cs' was never set and it did not didn't impose a maximum value.
>
> To reflect this hardware limitation in the device tree, the binding
> enforces that the 'num-cs' property cannot exceed 1 unless additional
> CS lines are explicitly defined using GPIO descriptors.
>
> Fixes: 2da187304e55 ("spi: add bindings for microchip mpfs spi")
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 29 +++++++++++++++++--
> 1 file changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> index 74a817cc7d94..ffa8d1b48f8b 100644
> --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> @@ -13,9 +13,6 @@ description:
> maintainers:
> - Conor Dooley <conor.dooley@microchip.com>
I provided the conditions below, so it's maybe a little disingenuous for
me to provide a review from a dt-bindings correctness point of view, but
then again I am the one listed as a maintainer for this particular
binding and what's being done here does match the hardware, so:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
>
> -allOf:
> - - $ref: spi-controller.yaml#
> -
> properties:
> compatible:
> oneOf:
> @@ -43,6 +40,32 @@ required:
> - interrupts
> - clocks
>
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: microchip,mpfs-spi
> + then:
> + properties:
> + num-cs:
> + default: 1
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: microchip,mpfs-spi
> + not:
> + required:
> + - cs-gpios
> + then:
> + properties:
> + num-cs:
> + maximum: 1
> +
> unevaluatedProperties: false
>
> examples:
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2024-05-14 17:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-14 10:45 [PATCH v2 0/3] Add support for GPIO based CS Prajna Rajendra Kumar
2024-05-14 10:45 ` [PATCH v2 1/3] spi: dt-bindings: Add num-cs property for mpfs-spi Prajna Rajendra Kumar
2024-05-14 17:52 ` Conor Dooley [this message]
2024-05-14 10:45 ` [PATCH v2 2/3] spi: spi-microchip-core: Fix the number of chip selects supported Prajna Rajendra Kumar
2024-05-14 17:53 ` Conor Dooley
2024-05-14 10:45 ` [PATCH v2 3/3] spi: spi-microchip-core: Add support for GPIO based CS Prajna Rajendra Kumar
2024-05-14 17:57 ` Conor Dooley
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