From: Roman Beranek <roman.beranek@prusa3d.cz>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Emil Lenngren <emil.lenngren@gmail.com>,
Pascal Roeleven <dev@pascalroeleven.nl>,
Lee Jones <lee.jones@linaro.org>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com
Subject: [PATCH 5/6] pwm: sun4i: shorten the delay to 2 cycles
Date: Mon, 31 May 2021 06:46:07 +0200 [thread overview]
Message-ID: <20210531044608.1006024-6-roman.beranek@prusa3d.com> (raw)
In-Reply-To: <20210531044608.1006024-1-roman.beranek@prusa3d.com>
As Emil Lenngren has previously shown, actually only 1-2 cycles of
the prescaler-divided clock are necessary to pass before the PWM turns
off (instead of a full period). I was able to reproduce his observation
on a A64 using a logic analyzer.
Suggested-by: Emil Lenngren <emil.lenngren@gmail.com>
Suggested-by: Pascal Roeleven <dev@pascalroeleven.nl>
Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
---
drivers/pwm/pwm-sun4i.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 8218173ce3f6..6ab06b9749d0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -71,7 +71,7 @@ static const u32 prescaler_table[] = {
72000,
0,
0,
- 0, /* Actually 1 but tested separately */
+ 1, /* Tested separately */
};
struct sun4i_pwm_data {
@@ -240,7 +240,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_state cstate;
u32 ctrl, duty = 0, period = 0, val;
int ret;
- unsigned int prescaler = 0;
+ unsigned int cycle_ns, current_prescaler, prescaler = 0;
bool bypass;
pwm_get_state(pwm, &cstate);
@@ -277,7 +277,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
}
- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+ current_prescaler = PWM_REG_PRESCAL(ctrl, pwm->hwpwm);
+ if (current_prescaler != prescaler) {
/* Prescaler changed, the clock has to be gated */
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
@@ -308,8 +309,10 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return 0;
}
- /* We need a full period to elapse before disabling the channel. */
- fsleep(cstate.period / NSEC_PER_USEC + 1);
+ /* We need to wait 1-2 cycles before disabling the channel. */
+ cycle_ns = DIV_ROUND_UP(NSEC_PER_SEC, clk_get_rate(sun4i_pwm->clk))
+ * prescaler_table[current_prescaler];
+ fsleep(DIV_ROUND_UP(cycle_ns * 2, NSEC_PER_USEC));
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
--
2.31.1
next prev parent reply other threads:[~2021-05-31 4:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-31 4:46 [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Roman Beranek
2021-05-31 4:46 ` [PATCH 1/6] pwm: sun4i: enable clk prior to getting its rate Roman Beranek
2021-06-07 8:00 ` Uwe Kleine-König
2021-05-31 4:46 ` [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay Roman Beranek
2021-06-07 8:07 ` Uwe Kleine-König
2021-05-31 4:46 ` [PATCH 3/6] pwm: sun4i: replace spinlock with a mutex Roman Beranek
2021-05-31 4:46 ` [PATCH 4/6] pwm: sun4i: simplify calculation of the delay time Roman Beranek
2021-05-31 4:46 ` Roman Beranek [this message]
2021-05-31 4:46 ` [PATCH 6/6] pwm: sun4i: don't delay if the PWM is already off Roman Beranek
2021-06-10 13:41 ` Pascal Roeleven
2021-05-31 19:07 ` [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Pascal Roeleven
2021-05-31 20:01 ` Emil Lenngren
2021-05-31 20:20 ` Pascal Roeleven
2021-06-08 12:28 ` Pascal Roeleven
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