From: 'Christoph Hellwig' <hch@lst.de>
To: David Laight <David.Laight@ACULAB.COM>
Cc: "'Christoph Hellwig'" <hch@lst.de>, "Guo Ren" <guoren@kernel.org>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Drew Fustini" <drew@beagleboard.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"wefu@redhat.com" <wefu@redhat.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-arch <linux-arch@vger.kernel.org>,
"linux-sunxi@lists.linux.dev" <linux-sunxi@lists.linux.dev>,
"Guo Ren" <guoren@linux.alibaba.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Benjamin Koch" <snowball@c3pb.de>,
"Matteo Croce" <mcroce@linux.microsoft.com>,
"Wei Fu" <tekkamanninja@gmail.com>
Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support
Date: Tue, 8 Jun 2021 17:32:03 +0200 [thread overview]
Message-ID: <20210608153203.GA6802@lst.de> (raw)
In-Reply-To: <2db975b5f24149b19191120b9f0f506b@AcuMS.aculab.com>
On Tue, Jun 08, 2021 at 03:00:17PM +0000, David Laight wrote:
> It is almost impossible to interface to many ethernet chips without
> either coherent or uncached memory for the descriptor rings.
> The status bits on the transmit ring are particularly problematic.
>
> The receive ring can be done with writeback+invalidate provided you
> fill a cache line at a time.
It is horrible, but it has been done. Take a look at:
drivers/net/ethernet/i825xx/lasi_82596.c and
drivers/net/ethernet/seeq/sgiseeq.c
next prev parent reply other threads:[~2021-06-08 15:32 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-19 5:04 [PATCH RFC 0/3] riscv: Add DMA_COHERENT support guoren
2021-05-19 5:04 ` [PATCH RFC 1/3] riscv: pgtable.h: Fixup _PAGE_CHG_MASK usage guoren
2021-05-19 5:04 ` [PATCH RFC 2/3] riscv: Add DMA_COHERENT for custom PTE attributes guoren
2021-05-19 5:04 ` [PATCH RFC 3/3] riscv: Add SYNC_DMA_FOR_CPU/DEVICE for DMA_COHERENT guoren
2021-05-19 6:32 ` Guo Ren
2021-05-19 5:20 ` [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Christoph Hellwig
2021-05-19 5:48 ` Guo Ren
2021-05-19 5:55 ` Christoph Hellwig
2021-05-19 6:09 ` Guo Ren
2021-05-19 6:44 ` Drew Fustini
2021-05-19 6:53 ` Christoph Hellwig
2021-05-20 1:45 ` Guo Ren
2021-05-20 5:48 ` Christoph Hellwig
2021-06-06 18:14 ` Nick Kossifidis
2021-06-07 0:04 ` Guo Ren
2021-06-07 2:16 ` Nick Kossifidis
2021-06-07 3:19 ` Guo Ren
2021-06-07 6:27 ` Christoph Hellwig
2021-06-07 6:41 ` Guo Ren
2021-06-07 6:51 ` Christoph Hellwig
2021-06-07 7:46 ` Guo Ren
2021-06-08 15:00 ` David Laight
2021-06-08 15:32 ` 'Christoph Hellwig' [this message]
2021-06-08 16:11 ` David Laight
2021-06-07 8:35 ` Nick Kossifidis
2021-06-09 3:28 ` Guo Ren
2021-06-09 6:05 ` Jisheng Zhang
2021-06-09 9:45 ` Nick Kossifidis
2021-06-09 12:43 ` Guo Ren
2021-05-19 6:05 ` Guo Ren
2021-05-19 6:06 ` Christoph Hellwig
2021-05-19 6:11 ` Guo Ren
2021-05-19 6:54 ` Drew Fustini
2021-05-19 6:56 ` Christoph Hellwig
2021-05-19 7:14 ` Anup Patel
2021-05-19 8:25 ` Damien Le Moal
2021-05-20 1:47 ` Guo Ren
2021-05-20 1:59 ` Guo Ren
2021-05-22 0:36 ` Guo Ren
2021-05-30 0:30 ` Palmer Dabbelt
2021-06-03 4:13 ` Palmer Dabbelt
2021-06-03 6:00 ` Anup Patel
2021-06-03 15:39 ` Palmer Dabbelt
2021-06-04 9:02 ` David Laight
2021-06-04 9:53 ` Arnd Bergmann
2021-06-04 14:47 ` Guo Ren
2021-06-04 16:12 ` Palmer Dabbelt
2021-06-04 21:26 ` Arnd Bergmann
2021-06-04 22:10 ` Palmer Dabbelt
2021-06-08 12:26 ` Guo Ren
2021-06-06 17:11 ` Guo Ren
2021-06-07 3:38 ` Anup Patel
2021-06-07 4:22 ` Guo Ren
2021-06-07 4:47 ` Anup Patel
2021-06-07 5:08 ` Guo Ren
2021-06-07 5:13 ` Guo Ren
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