From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF62471 for ; Thu, 20 May 2021 01:47:56 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 6A89B61279 for ; Thu, 20 May 2021 01:47:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1621475276; bh=poKYit/QMpU4dKJNKCzvxCXd10ycTg0LVovaKwHdVJU=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=O/x0LyiHKaXRHAHnix8Nv4+NwnU8XbzIAYPrRmgBkgKE5WuFEZlElAeQ0/x4E72+I oq+W1pFg/nSfT9fgfq3sPXU/rWOQo6P20vPJa/8IdNqGhrlPgbLqIZ24inzbIviBXl rPX0OUVtTu3qQv4vlVtuKDRAADMTpAAeoSnbB0wA7U1xrhLPWkD2HV7J0SKmDWUEBl 1lKfUJA6oXuvtE7R4iDGWMs7XZ4idntGYO8L69cW01UrgMuAuYqvgrPuW9iBsTNcLr NdIRxZAQeZWE/UN/vWMe5YGNm0T+3Fs4KsJ9KBX6xK7XzsBIJ6HbOLg8mjoKE1r3S2 ZZenF0FOdB45Q== Received: by mail-lf1-f48.google.com with SMTP id z13so21993391lft.1 for ; Wed, 19 May 2021 18:47:56 -0700 (PDT) X-Gm-Message-State: AOAM531fAIzN2pWdTLhp+4ZWcReSnmNEvK7T0ilLllBCgiIQ9imZRucQ uHRBjH95JR8jXV4vhXHf5N6aTKLLo1/9DQzFoN8= X-Google-Smtp-Source: ABdhPJy3NQHcs2Ir3IlcgG3aACIm8RSgvE2z8dE72bBss58+GSqw1LTUF9Ebe2CYmIkUeJauoGs+8f7zg55rxVr/uFI= X-Received: by 2002:a19:c49:: with SMTP id 70mr1686096lfm.555.1621475274744; Wed, 19 May 2021 18:47:54 -0700 (PDT) X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519060617.GA28397@lst.de> <20210519065431.GB3076809@x1> In-Reply-To: From: Guo Ren Date: Thu, 20 May 2021 09:47:43 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support To: Anup Patel Cc: Drew Fustini , Christoph Hellwig , Anup Patel , Palmer Dabbelt , wefu@redhat.com, =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley Content-Type: text/plain; charset="UTF-8" On Wed, May 19, 2021 at 3:15 PM Anup Patel wrote: > > On Wed, May 19, 2021 at 12:24 PM Drew Fustini wrote: > > > > On Wed, May 19, 2021 at 08:06:17AM +0200, Christoph Hellwig wrote: > > > On Wed, May 19, 2021 at 02:05:00PM +0800, Guo Ren wrote: > > > > Since the existing RISC-V ISA cannot solve this problem, it is better > > > > to provide some configuration for the SOC vendor to customize. > > > > > > We've been talking about this problem for close to five years. So no, > > > if you don't manage to get the feature into the ISA it can't be > > > supported. > > > > Isn't it a good goal for Linux to support the capabilities present in > > the SoC that a currently being fab'd? > > > > I believe the CMO group only started last year [1] so the RV64GC SoCs > > that are going into mass production this year would not have had the > > opporuntiy of utilizing any RISC-V ISA extension for handling cache > > management. > > The current Linux RISC-V policy is to only accept patches for frozen or > ratified ISA specs. > (Refer, Documentation/riscv/patch-acceptance.rst) > > This means even if emulate CMO instructions in OpenSBI, the Linux > patches won't be taken by Palmer because CMO specification is > still in draft stage. How do you think about sbi_ecall(SBI_EXT_DMA, SBI_DMA_SYNC, start, size, dir, 0, 0, 0); ? thx > > Also, we all know how much time it takes for RISCV international > to freeze some spec. Judging by that we are looking at another > 3-4 years at minimum. > > Regards, > Anup -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/