From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: [PATCH 12/19] PCI: cadence: Use bridge resources for outbound window setup Date: Tue, 21 Jul 2020 20:25:07 -0600 Message-ID: <20200722022514.1283916-13-robh@kernel.org> References: <20200722022514.1283916-1-robh@kernel.org> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200722022514.1283916-1-robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Bjorn Helgaas , Lorenzo Pieralisi Cc: Fabio Estevam , Gustavo Pimentel , Heiko Stuebner , Hou Zhiqiang , Jingoo Han , Jonathan Hunter , Karthikeyan Mitran , Linus Walleij , Lucas Stach , Marek Vasut , Michal Simek , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Richard Zhu , Ryder Lee , Sascha Hauer , Shawn Guo , Shawn Lin List-Id: linux-tegra@vger.kernel.org Instead of parsing 'ranges' from DT again, use the bridge window resources. Cc: Tom Joseph Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../controller/cadence/pcie-cadence-host.c | 37 ++++++++----------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 84aaf8834e11..f485c0405fb5 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -104,16 +104,14 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); struct resource *mem_res = pcie->mem_res; struct resource *bus_range = rc->bus_range; struct resource *cfg_res = rc->cfg_res; - struct device *dev = pcie->dev; - struct device_node *np = dev->of_node; - struct of_pci_range_parser parser; - struct of_pci_range range; + struct resource_entry *entry; u32 addr0, addr1, desc1; u64 cpu_addr; - int r, err; + int r; /* * Reserve region 0 for PCI configure space accesses: @@ -132,25 +130,22 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1); - err = of_pci_range_parser_init(&parser, np); - if (err) - return err; - r = 1; - for_each_of_pci_range(&parser, &range) { - bool is_io; - - if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM) - is_io = false; - else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) - is_io = true; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res = entry->res; + u64 pci_addr = res->start - entry->offset; + + if (resource_type(res) == IORESOURCE_IO) + cdns_pcie_set_outbound_region(pcie, 0, r, true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); else - continue; + cdns_pcie_set_outbound_region(pcie, 0, r, false, + res->start, + pci_addr, + resource_size(res)); - cdns_pcie_set_outbound_region(pcie, 0, r, is_io, - range.cpu_addr, - range.pci_addr, - range.size); r++; } -- 2.25.1