From: Luca Ceresoli <luca.ceresoli@bootlin.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Sowjanya Komatineni <skomatineni@nvidia.com>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Dmitry Osipenko <digetx@gmail.com>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>
Cc: Luca Ceresoli <luca.ceresoli@bootlin.com>,
linux-media@vger.kernel.org, linux-tegra@vger.kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>,
Richard Leitner <richard.leitner@skidata.com>
Subject: [RESEND PATCH v4 19/21] staging: media: tegra-video: add hooks for planar YUV and H/V flip
Date: Thu, 9 Mar 2023 15:43:18 +0100 [thread overview]
Message-ID: <20230309144320.2937553-20-luca.ceresoli@bootlin.com> (raw)
In-Reply-To: <20230309144320.2937553-1-luca.ceresoli@bootlin.com>
Tegra20 supports planar YUV422 capture, which can be implemented by writing
U and V base address registers in addition to the "main" base buffer
address register.
It also supports H and V flip, which among others requires to write the
start address (i.e. the 1st offset to write, at the end of the buffer or
line) in more registers for Y and, for planar formats, U and V.
Add minimal hooks in VI to allow per-SoC optional support to those
features:
- variables in struct tegra_vi for the U and V buffer base offsets
- variables in struct tegra_vi for the Y, U and V buffer start offsets
- an optional per-soc VI operation to compute those values on queue setup
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
---
Changed in v4:
- Added review tags
No changes in v3
No changes in v2
---
drivers/staging/media/tegra-video/vi.c | 4 ++++
drivers/staging/media/tegra-video/vi.h | 14 ++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c
index 760606c65a97..4a066b61ab8e 100644
--- a/drivers/staging/media/tegra-video/vi.c
+++ b/drivers/staging/media/tegra-video/vi.c
@@ -92,6 +92,7 @@ tegra_get_format_by_fourcc(struct tegra_vi *vi, u32 fourcc)
/*
* videobuf2 queue operations
*/
+
static int tegra_channel_queue_setup(struct vb2_queue *vq,
unsigned int *nbuffers,
unsigned int *nplanes,
@@ -107,6 +108,9 @@ static int tegra_channel_queue_setup(struct vb2_queue *vq,
sizes[0] = chan->format.sizeimage;
alloc_devs[0] = chan->vi->dev;
+ if (chan->vi->ops->channel_queue_setup)
+ chan->vi->ops->channel_queue_setup(chan);
+
return 0;
}
diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h
index d5e1ed4217e0..0503eb678556 100644
--- a/drivers/staging/media/tegra-video/vi.h
+++ b/drivers/staging/media/tegra-video/vi.h
@@ -47,6 +47,7 @@ struct tegra_vi_channel;
* @channel_host1x_syncpt_free: free all synchronization points
* @vi_fmt_align: modify `pix` to fit the hardware alignment
* requirements and fill image geometry
+ * @channel_queue_setup: additional operations at the end of vb2_ops::queue_setup
* @vi_start_streaming: starts media pipeline, subdevice streaming, sets up
* VI for capture and runs capture start and capture finish
* kthreads for capturing frames to buffer and returns them back.
@@ -58,6 +59,7 @@ struct tegra_vi_ops {
int (*channel_host1x_syncpt_init)(struct tegra_vi_channel *chan);
void (*channel_host1x_syncpt_free)(struct tegra_vi_channel *chan);
void (*vi_fmt_align)(struct v4l2_pix_format *pix, unsigned int bpp);
+ void (*channel_queue_setup)(struct tegra_vi_channel *chan);
int (*vi_start_streaming)(struct vb2_queue *vq, u32 count);
void (*vi_stop_streaming)(struct vb2_queue *vq);
};
@@ -148,6 +150,12 @@ struct tegra_vi {
* @queue: vb2 buffers queue
* @sequence: V4L2 buffers sequence number
*
+ * @addr_offset_u: U plane base address, relative to buffer base address (only for planar)
+ * @addr_offset_v: V plane base address, relative to buffer base address (only for planar)
+ * @start_offset: 1st Y byte to write, relative to buffer base address (for H/V flip)
+ * @start_offset_u: 1st U byte to write, relative to buffer base address (for H/V flip)
+ * @start_offset_v: 1st V byte to write, relative to buffer base address (for H/V flip)
+ *
* @capture: list of queued buffers for capture
* @start_lock: protects the capture queued list
* @done: list of capture done queued buffers
@@ -187,6 +195,12 @@ struct tegra_vi_channel {
struct vb2_queue queue;
u32 sequence;
+ unsigned int addr_offset_u;
+ unsigned int addr_offset_v;
+ unsigned int start_offset;
+ unsigned int start_offset_u;
+ unsigned int start_offset_v;
+
struct list_head capture;
/* protects the capture queued list */
spinlock_t start_lock;
--
2.34.1
next prev parent reply other threads:[~2023-03-09 14:46 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 14:42 [RESEND PATCH v4 00/21] Add Tegra20 parallel video input capture Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 01/21] dt-bindings: display: tegra: add Tegra20 VIP Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 02/21] dt-bindings: display: tegra: vi: add 'vip' property and example Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 03/21] staging: media: tegra-video: fix .vidioc_enum_fmt_vid_cap to return all formats Luca Ceresoli
2023-03-29 11:16 ` Hans Verkuil
2023-03-29 11:56 ` Hans Verkuil
2023-04-04 14:12 ` Luca Ceresoli
2023-04-05 2:30 ` Laurent Pinchart
2023-04-05 8:31 ` Luca Ceresoli
2023-04-05 8:50 ` Hans Verkuil
2023-04-05 9:28 ` Thierry Reding
2023-04-05 14:30 ` Laurent Pinchart
2023-03-09 14:43 ` [RESEND PATCH v4 04/21] staging: media: tegra-video: improve documentation of tegra_video_format fields Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 05/21] staging: media: tegra-video: document tegra_channel_get_remote_source_subdev Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 06/21] staging: media: tegra-video: fix typos in comment Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 07/21] staging: media: tegra-video: improve error messages Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 08/21] staging: media: tegra-video: slightly simplify cleanup on errors Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 09/21] staging: media: tegra-video: move private struct declaration to C file Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 10/21] staging: media: tegra-video: move tegra210_csi_soc " Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 11/21] staging: media: tegra-video: remove unneeded include Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 12/21] staging: media: tegra-video: Kconfig: allow TPG only on Tegra210 Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 13/21] staging: media: tegra-video: move tegra_channel_fmt_align to a per-soc op Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 14/21] staging: media: tegra-video: move default format to soc-specific data Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 15/21] staging: media: tegra-video: move MIPI calibration calls from VI to CSI Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 16/21] staging: media: tegra-video: add a per-soc enable/disable op Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 17/21] staging: media: tegra-video: move syncpt init/free to a per-soc op Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 18/21] staging: media: tegra-video: add syncpts for Tegra20 to struct tegra_vi Luca Ceresoli
2023-03-09 14:43 ` Luca Ceresoli [this message]
2023-03-09 14:43 ` [RESEND PATCH v4 20/21] staging: media: tegra-video: add H/V flip controls Luca Ceresoli
2023-03-09 14:43 ` [RESEND PATCH v4 21/21] staging: media: tegra-video: add support for Tegra20 parallel input Luca Ceresoli
2023-03-22 9:14 ` [RESEND PATCH v4 00/21] Add Tegra20 parallel video input capture Luca Ceresoli
2023-03-22 9:29 ` Hans Verkuil
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