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[209.85.208.54]) by smtp.gmail.com with ESMTPSA id gj14-20020a170906e10e00b008df7d2e122dsm6346841ejb.45.2023.03.07.09.48.50 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Mar 2023 09:48:50 -0800 (PST) Received: by mail-ed1-f54.google.com with SMTP id o12so55624688edb.9 for ; Tue, 07 Mar 2023 09:48:50 -0800 (PST) X-Received: by 2002:a50:cd94:0:b0:4c2:1a44:642e with SMTP id p20-20020a50cd94000000b004c21a44642emr8679892edi.5.1678211329875; Tue, 07 Mar 2023 09:48:49 -0800 (PST) MIME-Version: 1.0 References: <20230303231133.1486085-1-eranian@google.com> <20230306120106.GE1267364@hirez.programming.kicks-ass.net> <20230307113545.GB2017917@hirez.programming.kicks-ass.net> In-Reply-To: <20230307113545.GB2017917@hirez.programming.kicks-ass.net> From: Linus Torvalds Date: Tue, 7 Mar 2023 09:48:33 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] x86/resctrl: avoid compiler optimization in __resctrl_sched_in To: Peter Zijlstra Cc: Nick Desaulniers , Stephane Eranian , linux-kernel@vger.kernel.org, tony.luck@intel.com, reinette.chatre@intel.com, fenghua.yu@intel.com, peternewman@google.com, james.morse@arm.com, babu.moger@amd.com, ananth.narayan@amd.com, vschneid@redhat.com, Nathan Chancellor , clang-built-linux , Borislav Petkov , "H. Peter Anvin" , linux-toolchains@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-toolchains@vger.kernel.org On Tue, Mar 7, 2023 at 3:36=E2=80=AFAM Peter Zijlstra wrote: > > > I don't have a satisfactory answer yet, but am looking into this. > > Oh, geez, what a twisty tale that... So Linus knew back in '09 that "p" > was icky, but it sorta was the only thing and it 'worked' -- until now > :/ Yeah, so 'p' definitely is about the pointer, and I do worry that it is only a dependency on exactly that - not the memory behind it. I have this dim memory about us having talked about this with some gcc person, and coming to the conclusion that it was all fine, but I suspect it was in some very specific case where it might have been fine for other reasons. > Is there a way to explicitly order these things? barrier() obviously > isn't going to help here. So one "asm volatile" should always be ordered wrt another "asm volatile". I have this other dim memory of it not even being clear whether "asm" and "asm volatile" are ordered. I don't think they necessarily are (with the obvious caveat that an asm without any arguments - a so-called "basic asm" - is always volatile whether the "volatile" is there or not). I have a lot of dim memories, in other words. Should that worry me? And then there's the "memory" clobber, of course. But both of those are also going to disable CSE. I do think that percpu_stable_op can use "p", but only when the value is *truly* stable and there is no question about it being moved around things that might modify it. Linus