From: Crystal Guo <crystal.guo@mediatek.com>
To: <linux@roeck-us.net>, <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <srv_heupstream@mediatek.com>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-watchdog@vger.kernel.org>,
<seiya.wang@mediatek.com>, <erin.lo@mediatek.com>,
Crystal Guo <crystal.guo@mediatek.com>
Subject: [v2,2/3] dt-binding: mt8192: add toprgu reset-controller head file
Date: Wed, 29 Jul 2020 18:02:01 +0800 [thread overview]
Message-ID: <1596016922-13184-3-git-send-email-crystal.guo@mediatek.com> (raw)
In-Reply-To: <1596016922-13184-1-git-send-email-crystal.guo@mediatek.com>
add toprgu reset-controller head file for MT8192 platform
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
.../dt-bindings/reset-controller/mt8192-resets.h | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8192-resets.h
diff --git a/include/dt-bindings/reset-controller/mt8192-resets.h b/include/dt-bindings/reset-controller/mt8192-resets.h
new file mode 100644
index 0000000..be9a7ca
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8192-resets.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yong Liang <yong.liang@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
+
+#define MT8192_TOPRGU_MM_SW_RST 1
+#define MT8192_TOPRGU_MFG_SW_RST 2
+#define MT8192_TOPRGU_VENC_SW_RST 3
+#define MT8192_TOPRGU_VDEC_SW_RST 4
+#define MT8192_TOPRGU_IMG_SW_RST 5
+#define MT8192_TOPRGU_MD_SW_RST 7
+#define MT8192_TOPRGU_CONN_SW_RST 9
+#define MT8192_TOPRGU_CONN_MCU_SW_RST 12
+#define MT8192_TOPRGU_IPU0_SW_RST 14
+#define MT8192_TOPRGU_IPU1_SW_RST 15
+#define MT8192_TOPRGU_AUDIO_SW_RST 17
+#define MT8192_TOPRGU_CAMSYS_SW_RST 18
+#define MT8192_TOPRGU_MJC_SW_RST 19
+#define MT8192_TOPRGU_C2K_S2_SW_RST 20
+#define MT8192_TOPRGU_C2K_SW_RST 21
+#define MT8192_TOPRGU_PERI_SW_RST 22
+#define MT8192_TOPRGU_PERI_AO_SW_RST 23
+
+#define MT8192_TOPRGU_SW_RST_NUM 23
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-07-29 10:02 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 10:01 [v2,0/3] add watchdog support for mt8192 Crystal Guo
2020-07-29 10:02 ` [v2,1/3] dt-binding: mediatek: mt8192: update mtk-wdt document Crystal Guo
2020-07-29 10:18 ` Matthias Brugger
2020-07-30 1:35 ` Crystal Guo
2020-07-30 9:02 ` Matthias Brugger
2020-07-29 10:02 ` Crystal Guo [this message]
2020-07-30 9:04 ` [v2,2/3] dt-binding: mt8192: add toprgu reset-controller head file Matthias Brugger
2020-07-29 10:02 ` [v2,3/3] watchdog: mt8192: add wdt support Crystal Guo
2020-07-30 9:03 ` Matthias Brugger
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