Re: [PATCH v2 8/8] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile

From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Seiya Wang <seiya.wang@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Jonathan Cameron <jic23@kernel.org>,
	"Lars-Peter Clausen" <lars@metafoo.de>,
	Peter Meerwald-Stadler <pmeerw@pmeerw.net>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Vinod Koul <vkoul@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Wim Van Sebroeck <wim@linux-watchdog.org>,
	Guenter Roeck <linux@roeck-us.net>,
	"Enric Balletbo i Serra" <enric.balletbo@collabora.com>,
	Hsin-Yi Wang <hsinyi@chromium.org>,
	Fabien Parent <fparent@baylibre.com>,
	Sean Wang <sean.wang@mediatek.com>,
	Zhiyong Tao <zhiyong.tao@mediatek.com>,
	"Chaotian Jing" <chaotian.jing@mediatek.com>,
	Wenbin Mei <wenbin.mei@mediatek.com>,
	Stanley Chu <stanley.chu@mediatek.com>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-iio@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-serial@vger.kernel.org>, <linux-watchdog@vger.kernel.org>,
	<srv_heupstream@mediatek.com>
Subject: Re: [PATCH v2 8/8] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
Date: Tue, 23 Mar 2021 10:46:02 +0800	[thread overview]
Message-ID: <1616467562.11286.6.camel@mhfsdcap03> (raw)
In-Reply-To: <20210319023427.16711-10-seiya.wang@mediatek.com>

On Fri, 2021-03-19 at 10:34 +0800, Seiya Wang wrote:
> Add basic chip support for Mediatek MT8195
> 
> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/Makefile       |   1 +
>  arch/arm64/boot/dts/mediatek/mt8195-evb.dts |  29 ++
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi    | 464 ++++++++++++++++++++++++++++
>  3 files changed, 494 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index deba27ab7657..aee4b9715d2f 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
>  dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
> new file mode 100644
> index 000000000000..82bb10e9a531
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + * Author: Seiya Wang <seiya.wang@mediatek.com>
> + */
> +/dts-v1/;
> +#include "mt8195.dtsi"
> +
[...]
> +		nor_flash: nor@1132c000 {
> +			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
> +			reg = <0 0x1132c000 0 0x1000>;
> +			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "spi", "sf";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		u3phy2: t-phy@11c40000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11c40000 0x700>;
> +			status = "disabled";
> +
> +			u2port2: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		u3phy3: t-phy@11c50000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11c50000 0x700>;
> +			status = "disabled";
> +
> +			u2port3: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		u3phy1: t-phy@11e30000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11e30000 0xe00>;
> +			status = "disabled";
> +
> +			u2port1: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port1: usb-phy@700 {
> +				reg = <0x700 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		u3phy0: t-phy@11e40000 {
> +			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0 0x11e40000 0xe00>;
> +			status = "disabled";
> +
> +			u2port0: usb-phy@0 {
> +				reg = <0x0 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +
> +			u3port0: usb-phy@700 {
> +				reg = <0x700 0x700>;
> +				clocks = <&clk26m>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
> +		ufsphy: phy@11fa0000 {
> +			compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
> +			reg = <0 0x11fa0000 0 0xc000>;
> +			clocks = <&clk26m>, <&clk26m>;
> +			clock-names = "unipro", "mp";
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +	};
> +};
phy part:

Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Thank you